Delta-sigma anti-aliasing filter with mode suppression circuit

The design of anti-aliasing filters for delta-sigma data converters is significantly different from the design approach for SAR (successive approximation register) or pipeline (high-speed) converters. With a SAR or pipeline converter, you have a system that evaluates one sample at a time. In either case, the analog signal is "grabbed" and stored in the converter's input capacitor array. These converters evaluate the stored signal and provide a digital representation for each sample. For both devices, the target frequency of the multi-order anti-aliasing filter is the Nyquist frequency of the converter. The 
 
input modulator of the delta-sigma converter samples the input analog signal multiple times at a high sampling rate (FS, Reference 1). The subsequent Sinc digital filter resamples a set of these modulator samples and converts them to a digital representation of the output. The conversion from a modulator sample string to a 24-bit digital code is much slower than the sampling rate of the delta-sigma input structure (FD, Reference 1). Therefore, the delta-sigma converter has two sampling rates (FS, FD). However, the target frequency of the first-order anti-aliasing filter is the output data rate FD. In Reference 1 you can find basic anti-aliasing filter design concepts for delta-sigma converters.

Figure 1 This complete filter attenuates the differential noise of RFLT/2 and CFLT, as well as the common-mode noise of CCM_P and CCM_N.

Note that the circuits and discussion in Reference 1 and Reference 2 address only the reduction of differential noise and are not concerned with the input impedance or common-mode noise of the converter.

Regarding the converter's input impedance, the capacitors at the delta-sigma converter's switched-capacitor inputs are continuously charged and discharged during the voltage measurement between AINP and AINN. These internal capacitors (CB, CA1, and CA2) are relatively small compared to the external circuitry. Therefore, its average input impedance appears resistive. The converter's capacitance and the modulator's slew rate determine this resistance.

To measure the common-mode input impedance of the structure in Figure 2, connect AINP and AINN together and measure the average current consumed by each pin during the conversion. To measure the differential input impedance, apply a differential signal to AINP and AINN and measure the average current flowing from the pin to VA. The common-mode and differential resistances can range from a few hundred kilo-ohms to a few hundred megohms. Their values ​​depend on the circuitry that follows the input switched capacitor structure inside the converter. The value of RFLT/2 must be at least 10 times lower than the input impedance of the converter.

The two common-mode capacitors CCM_P and CCM_N are used to attenuate high-frequency common-mode noise. The differential capacitor should be at least one order of magnitude larger than the common-mode capacitor because mismatching of the common-mode capacitors can cause differential noise.

Aliasing can occur if the input signal to any ADC contains frequencies above half the data rate. To prevent this, the input signal containing noise and interference components should be band-limited. The digital filter in the delta-sigma converter can provide some high-frequency noise attenuation, but the digital sinc filter cannot completely replace the anti-aliasing filter. When designing an input filter circuit, consider the interaction between the converter filter network and the input impedance.