Implementation of a Differential Delay Line ADC in a DC/DC Converter

Traditional DC/DC converters generally use analog control, which has the advantages of small size and low power consumption, but is easily affected by noise. Digitally controlled DC/DC converters are insensitive to process parameters and environment, control algorithms can be implemented through programming, are easy to integrate, and can greatly shorten the product development cycle.

1 DC/DC converter structure

The digital controller is mainly composed of an analog-to-digital converter (ADC), a digital compensator, and a digital pulse width modulator (DPWM). A commonly used digital controller is shown in Figure 1. The output voltage of the main circuit is compared with the reference voltage by the ADC and converted into a corresponding digital error signal. The digital compensator compensates for the error to obtain a given digital signal. The DPWM converts it into a time signal to control the on and off of the main circuit switch.

2 Delay Line ADC

The delay td of a logic gate in a standard CMOS process has the following relationship with the power supply voltage VDD:

Where K is a constant related to the device and process, and Vth is the threshold voltage of the MOS device. When VDD is greater than Vth, td can be regarded as inversely proportional to VDD.

The delay line ADC consists of a delay chain, a register group and a decoding circuit, and the structure is shown in Figure 2. A series of delay units constitute the delay chain. The structure of a feasible delay unit is shown in Figure 3. It is obtained by cascading an inverter and a NOR gate. Each delay unit has an input terminal, a reset terminal and an output terminal.

Given a start signal AD_Stan, a sampling pulse signal sample is generated after a certain time interval as the control signal of the D flip-flop. When the sampling signal is valid, the input signal of the D flip-flop is latched, and the output signal of the D flip-flop is sent to the decoding circuit to obtain the final error signal. Figure 4 is a timing diagram of the delay line ADC, assuming that n=8 in Figure 2. When the sampling signal is valid, the AD_Start signal is transmitted to the fifth delay unit, so q1~q5 outputs are 1, and q6~q8 outputs are 0. The larger the sampling voltage, the smaller the delay time td, the faster the signal propagates, and the more 1s in the output thermometer code. The decoding circuit then converts the thermometer code into the required binary code. The delay line ADC powers the delay chain through the input power supply, and determines the input size according to the delay time of the delay chain.

3 Differential Delay Line ADC

3.1 Differential Delay Line ADC Structure Analysis

The delay line ADC has a simple structure and low power consumption, but is easily affected by the process and temperature environment, and the sampling signal needs to be generated externally, which increases the complexity of the circuit. In addition, the delay of the sampling signal will affect the size of the ADC quantization level, making the system output difficult to stabilize.

The differential delay line structure is an improvement on the delay line structure, and the structure diagram is shown in Figure 5. The differential delay line ADC consists of two identical delay chains, the primary delay chain (Primary delay-line) and the reference delay chain (Reference delay-line). The reference delay chain can be copied from the primary delay chain. The two differential delay chains share a start signal AD_Start, so that the working states of the two delay chains are exactly the same. The two inputs of the differential delay chain are the sampling voltage Vsense and the reference.

The voltage Vref and Vsense must be less than Vref. According to the principle that the larger the voltage, the smaller the delay, the reference delay chain is propagated before the main delay chain. The D flip-flop connected to the main delay chain is turned on to sample the Vsense on the main delay chain. In this way, the sampled voltage is compared with the reference voltage, and the digital error signal required by the system is obtained through the decoding circuit.

The control signal of the differential delay line ADC is generated internally, which further simplifies the circuit structure. The differential input makes the sampling voltage and the reference voltage simultaneously affected by temperature and process deviation, reducing the delay deviation of the main delay chain.

3.2 Differential Delay Line ADC Modeling

Assume the number of delay units in the delay chain is N, and the delay time td is a function of VDD: td=td(VDD), then

That is, the conversion time Tc is a function of the resolution Vq, the delay time td and the slope of the delay function.

FIG6 is a curve showing the relationship between a single delay unit and VDD in a 0.13 μm CMOS process.

4 Design Method and Simulation Results

The delay unit has high requirements on precision and adopts a fully customized design, while the decoding circuit has low requirements on precision and adopts a design based on standard library units. The overall circuit uses Hsim for mixed analog-digital simulation.

During the design, the reference voltage is 1.5V, the operating frequency is 1.5MHz, the input voltage rises linearly from 0.7 to 1.5V, and the output is the decoded result, that is, the 6-bit digital signal e. For every 12.5mV increase or decrease in Vsense, e increases or decreases by "1", but the maximum value of e is 63. Figure 7 shows the input and output curves of the differential delay line ADC under the 0.13μm CMOS process. It can be seen that the output of the differential delay line ADC has no obvious offset, zero input corresponds to zero output, and the linearity is good.

5 Conclusion

The differential delay line ADC circuit has a simple structure, does not require an external circuit to generate a control signal, and can offset some process deviations. The ADC has a fast conversion rate and low power consumption, and is suitable for use in high-frequency digital DC/DC converters.