Introduction to the design of 5.0 to 6.5W Ethernet power supply DC/DC converter

This article describes a Power over Ethernet (PoE) solution using ON Semiconductor's NCP1031 series of monolithic high-voltage switching regulators (with internal MOSFETs). This application note details how to build a low-cost, high-efficiency, 5.0V DC power supply with an output power of 5.0 to 6.5W (output power depends on the conversion mode - see the DC/DC converter operation theory described below), which also includes the input circuitry associated with responding to the PoE detection and classification protocol. ON Semiconductor can provide a demonstration PCB of the relevant circuit upon user request.

PoE Background

As the IEEE802.3AF standard, it is now possible to feed power to Ethernet communication devices through Ethernet data transmission lines, as long as the terminal power requirement is less than 13W. Details on DC power transmission and related terminology can be found in this IEEE document. PoE consists of two power entities, namely power supply equipment (PSE) and powered device (PD). PSE generally provides a nominal DC voltage of 48V to the LAN cable, while PD is a small DC/DC converter at the other end of the cable that can convert 48V into logic levels such as 5.0Vdc or 3.3Vdc for communication circuits. PD should be able to operate at a maximum average input power of 12.95W and can withstand input voltages in the range of 36 to 57Vdc. A specific "protocol" is also required to implement PD detection (signature mode) and classification based on maximum power level (classification mode).

Signature detection: The upstream PSE device detects the PD by delivering two different voltages in the range of 2.8 to 10Vdc to the PD input. If the PD impedance measured by the V/I slope is greater than 23.7kΩ and less than 26.25kΩ, the PD device is considered to be present. If the impedance is less than 15kΩ or greater than 33kΩ, the PD is considered not present and no further voltage is applied.

Classification mode: To classify the PD according to the target power level, the PSE also delivers a voltage between 14.5 and 20.5 Vdc to the PD. The PD's class is determined based on the current drawn by the PD at this voltage, as summarized in the table below.

Additional input features

In addition to the signature and classification circuitry, the PD must also include circuitry to limit the inrush current from the PSE to 400mA when the input voltage arrives, and to prevent any quiescent current or impedance caused by the DC/DC converter from being ignored during the signature and classification process.

Specific signature/classification circuit

Referring to the schematic in Figure 1, the input signature and classification circuit is designed around several discrete and low-cost ON Semiconductor devices, including the TL431 programmable reference circuit, 2N7002 signal level MOSFET, 2N5550 NPN transistor, NTD12N10 MOSFET and several Zener diodes and resistors and capacitors. To implement signature detection, a 24.9k resistor (R1) is placed directly at the input. It is important to note that during the signature detection phase, the input voltage is below 10V and the constant current source formed by U1, Q2 and R4 is turned off because the 9.1V breakdown voltage must be exceeded to complete the biasing of this circuit. Also note that the input switch MOSFET Q3, which is connected in series with the return leg of the DC/DC converter, is also turned off until the input voltage exceeds approximately 27V. This voltage is equal to the sum of the breakdown voltage of D2 and the gate threshold voltage of Q3.

Figure 1: Schematic diagram of a PoE powered device (PD).

As the voltage rises to the classification level, D1 will turn on when the voltage exceeds about 9.8V, the current source composed of U1, Q2 and resistor R4 is turned on, and the current is accurately controlled by the U1 reference voltage (2.5V) and the classification resistor R4.

Once the classification is complete and confirmed, the input voltage can jump to the nominal value of 48V. Once this voltage exceeds the sum of Q3's gate threshold and D2's breakdown voltage, Q3 begins to turn on. However, Q3 does not turn on suddenly, it immediately enters the linear region due to the RC time constant formed by R6 and C2. Immediate operation in the linear region can limit the inrush current because Q3 is equivalent to a resistor during this time. D3 clamps the voltage on Q3's gate to 15V, and R5 provides a discharge path for C2 when the input from the PSE is turned off. MOSFET tube Q1 also turns on at the same voltage as Q3, which turns off the U1/Q2 current source, thereby reducing the additional leakage current from the input.

How DC/DC Converters Work

The DC/DC converter is designed using ON Semiconductor's monolithic NCP1031 switching regulator chip (U2). At a maximum output power of 5.0W, the converter is configured as a discontinuous mode (DCM) flyback topology using a common TL431 and an optocoupler voltage feedback mechanism. Modifying the transformer design and the control loop compensation network to operate in a continuous conduction flyback mode of operation can increase the output power to 6.5W (1.3A). A differential mode π-type filter consisting of C3, L1, and C4 is used at the input.

When the undervoltage terminal of pin 6 exceeds 2.5V, the control chip starts to start. The resistor divider network composed of R7, R8 and R9 sets the undervoltage and overvoltage levels of the chip to 35V and 80V respectively. Pin 8 provides internal startup bias and drives the constant current source to charge the Vcc capacitor C7. Once U2 is turned on, the auxiliary coil of transformer T1 (pins 2, 3) provides working bias through diode D1 and resistor R11.

The voltage spike caused by the leakage inductance of T1 is clamped by the network composed of C5, D6 and R10. The actual power rating on R10 is a function of the primary to secondary leakage inductance of T1, and the lower the better. Capacitor C6 sets the switching frequency of the converter to about 220kHz.

Due to the need for secondary isolation, the TL431 (U4) is used as an error amplifier to form a voltage sensing and feedback circuit with an optocoupler (U3). The internal error amplifier in U2 has been disabled by grounding the voltage sense pin 3, and the amplifier output compensation node on pin 4 is used to control the pulse width through the optocoupler's light resistance. The sensed output voltage is divided down by R16 and R17 to the TL431's 2.5V reference level, and C9 and R15 set the closed-loop bandwidth and phase margin suitable for DCM operation. If configured for CCM flyback operation, additional components (C14, C15, and R12) are required to stabilize the feedback loop. C8 on the primary side provides noise decoupling and additional high-frequency roll-off performance to U2. This implementation provides output regulation better than 0.5% for both line and load variations, and closed-loop phase margin better than 50°C.

Output rectifier D5 is a 3A Schottky device for improved efficiency, and its output voltage is filtered by a π network consisting of C11, L2, and C12. Typical peak-to-peak noise and ripple at the filtered output are less than 100mV under all normal load and line conditions. C13 provides additional high-frequency noise attenuation. Typical input-to-output efficiency is about 75% under full load conditions (Figure 2). Higher efficiency can be achieved by replacing D5 with a MOSFET-based synchronous rectification circuit (ON Semiconductor's application note AND8127 details how to implement a simple synchronous rectification circuit for a flyback topology).

Figure 2: Efficiency vs. output power.

The overcurrent protection function is provided by the internal peak current limiting circuit in NCP1031. In a 25℃ environment, when the circuit is configured in CCM flyback mode, it can provide 1.3A continuous output current before the overcurrent and/or overtemperature limiting function is activated, and the surge current can be as high as 1.5A. When configured in discontinuous mode, the current is limited to about 1.0A, and the peak current can reach 1.2A.

Electromagnetic Design

The flyback transformer design for discontinuous mode is shown in Figure 3 and the transformer design for continuous mode is shown in Figure 4. In flyback transformer design, it is important to keep the windings in a single layer and evenly distributed over the window length of the core structure in order to minimize leakage inductance. This can be easily achieved in this case using a small EF16 ferrite core from Ferroxcube.

Figure 3a: Discontinuous mode flyback transformer description.

Figure 3: Discontinuous mode flyback transformer design.

Figure 4a: Continuous mode transformer description.

Figure 4: Continuous mode transformer design.

Discontinuous and continuous mode operation

Table 1: Ethernet power level classification.

In the discontinuous mode flyback operation, the inductor current drops to zero before the MOSFET switch is turned on again. This operation mode makes the output have the characteristics of a first-order filter network, so the feedback loop stabilization circuit is simple, a wide bandwidth can be obtained and good output transient response can be achieved. Unfortunately, this operation mode will produce a higher peak switch current and limit the output power of the circuit due to the internal current limit set point and the thermal protection circuit in the NCP1031. In the continuous current mode of operation, the MOSFET can return to the on state before the inductor current reaches zero, so the peak switch current is low and a higher output power can be obtained without the intervention of overcurrent protection. However, this operation mode also has a price, that is, the control loop bandwidth must be made lower, so the transient response to load and line changes is poor. The CCM operation mode will introduce a right half plane zero in the power topology response characteristics, which needs to be compensated by additional feedback components as shown in Figure 2 to obtain appropriate feedback stability. Since the output rectifier must be forced to turn off the rectification function at this time, CCM will also generate more electromagnetic interference.