Distributed Control System of Three-phase Inverter

In order to build a power electronic distributed control system based on PEBB, in addition to realizing the modularization of PEBB standard structure and control functions, the most important thing is to standardize signal distribution, network interface and communication protocol. Therefore, the division of control authority between HM, AM and SM is a key issue, which determines the communication requirements of different spatial and temporal distributions and determines the tasks performed by different managers.

The three-phase voltage source inverter is widely used, and its topology is universal. It is of typical significance to analyze its control system. According to the requirements of Figures 1 and 2, the control authority of the control system of the three-phase voltage source inverter is divided to realize its distributed control, as shown in Figure 3. The PB in the figure is composed of three groups of switch bridge arms. HM mainly includes a pulse generator, an AD conversion circuit and a protection circuit (environmental monitoring, fault detection), as well as a communication interface and a level conversion circuit.

AM is the control core of the whole system and must be able to realize complete control functions. As an example, the control functions of AM in Figure 3 include: angle observation, ABC/DQ conversion, current regulation, speed regulation, DQ/αβ conversion and SVM modulation. The whole control algorithm is a double closed-loop structure, with speed regulation as the outer loop and current regulation as the inner loop. At the same time, AM provides a communication mechanism with HM and other AMs. SM can use an industrial computer or a specially designed microprocessor + input (keyboard) + output (LCD screen). Regardless of the method, sufficient storage space must be configured to store various basic control algorithms for function settings during system initialization.

Interface I1 is selected between the pulse generator and the SVM modulator, and the data transmitted is mainly real-time data, including: current sampling, speed sampling, switch state vector and vector duty cycle. Interface I2 is selected at the input part of the load regulator, which is actually the interface between the speed regulator and SM; the data transmitted at interface I2 are mainly speed reference value and fault feedback signal, which are non-real-time data. Each interface can transmit signals bidirectionally, but the data volume, data format and refresh rate are different. The data transmitted by interfaces I1 and I2 are all digital variables.

The required channel bandwidth for each digital variable can be expressed as

B=Kd·fsw·nx. (1)

Where: Kd is the ratio of sampling time to transmission time, fSW is the sampling frequency, i.e. the refresh rate, and nx is the number of binary bits of the measured variable. It is generally assumed that the sampling frequency is the same as the switching frequency.

It should be noted that the switch state vector is a 3*n-order matrix, and the value range of each quantity in the matrix is ​​[0 1], which can be represented by only one binary digit. The number of binary digits required for the duty cycle (order vector), power switch fault signal, three current sampling values, and speed sampling value are all recorded as N0, then the bandwidth required by interface I1 is

B1=(3*n)·Kdl·fsw·1+N1·Kd1·fsw·N0. (2)

Where: N1 is the total number of sampled data in interface I1. Similarly, the channel bandwidth of interface I2 can be expressed as

B2=N2·Kd2·fSW·N0. (3)

Where: N2 is the total number of sampled data in interface I2, and the following parameters are taken: fsW=20kHz, No=12, Kd1=2, n=3 (n depends on different control strategies). Since the fault feedback signal and voltage reference rarely change, frequent sampling is not required, so Kd2=0.2 is taken. According to equations (2) and (3), the minimum channel transmission capacity (Mb/s) required for each interface of the three-phase voltage source inverter can be obtained, which are

B1=4.2; B2=0.096. (4)

The above formula shows that the farther the interface is from the main circuit, the less bandwidth is required. Based on this, it is possible to consider designing more control links within the HM, which will reduce the amount of data to be communicated by other interfaces. The bandwidth required for interface I1 is below 10Mb/s. Even if the start bit, address bit, check bit and other format bits are added during communication, the bandwidth required for I1 will not be very large. Therefore, this interface can be used as a physical interface between HM and AM. To realize communication between AMs at interface I1, the transmission of real-time data and non-real-time data must be considered at the same time; for real-time data, synchronous communication between AMs must be realized. Non-real-time data was not taken into account when calculating the bandwidth of interface I1, but it does not affect the statement of the problem.

The data communication volume of interface I2 is significantly reduced, generally less than 1Mb/s, and the data to be transmitted only includes configuration information and monitoring information. It can be used as an interface for system-level communication, that is, the physical interface between AM and SM. When building a large distributed control system, the communication between the master and slave SM can be easily realized through interface I2.