Power Architecture Factorized Power

In recent years, with the development of the electronics and data industries and the promotion of distributed power supply systems, the application of DC-DC converters has become more and more widespread. New microprocessors, memories, DSPs and ASICs tend to require low voltage and high current power supply. Facing the new generation of electronic devices and loads, the power supply industry faces major challenges. In addition to being able to output high current at low voltage, the products must also be small in size, light in weight, fast in dynamic response, low in noise and affordable in price. These demands have prompted the industry to re-examine existing technologies and architectures.

The evolution of power architecture (CPA)

Centralized power supply is the most basic power supply structure, which is simple and low cost. It concentrates the functions from the front end to the DC-DC conversion in one frame, reduces the board space occupied by the load point, avoids multiple power conversions in series, has better efficiency, and is relatively easy to handle heat dissipation and EMI problems. Designers also need to balance I2R power consumption and EMI to determine the distance between the power supply and the load. Although centralized power supply works well in many applications, it is not very suitable for applications that require low voltage and multiple load points.

Distributed Performance Architecture (DPA)

Since the advent of power modules in the 1980s, distributed architecture has been widely adopted and has become the most commonly used architecture. (Brick-type power modules have the three basic functions of DC-DC converters: isolation, voltage transformation and voltage regulation. Engineers can place the power module on the system circuit board and supply power close to the load. The distributed architecture is powered by a rougher DC bus (usually 48V or 300V), which is then converted into a suitable voltage by a DC-DC converter placed next to the system circuit board to power the load. This layout can improve the dynamic response of the system and avoid problems caused by low-voltage operation of the entire system.

The cost of distributed power supply is generally high, especially when there are many loads, which requires a large circuit board space. In addition, the functions of isolation, voltage transformation, voltage regulation, EMI filtering and input protection are repeated at each load point, which naturally increases the cost of the module.

Intermediate Bus Architecture (IBA)

The intermediate bus architecture (Figure 1) addresses the shortcomings of the distributed power architecture. It divides the isolation, transformation and regulation functions of the DC-DC converter into two devices. The IBC (intermediate bus converter) provides the transformation and isolation functions. The niPoL (non-isolated point-of-load converter) provides the regulation function. The IBC converts the semi-regulated distributed bus to an unregulated and isolated intermediate bus voltage (usually 12V) to power a series of niPoLs. The niPoL is close to the load and provides the transformation and regulation functions. The idea of ​​the IBA is to step down the bus voltage to a voltage slightly higher than the load point, and then the cheaper buck (niPoL) does the rest. The buck (niPoL) transmits a voltage to the load through the inductor, which is equal to the average of the voltages at the common terminals of the upper and lower switches, which is equal to the product of the duty cycle of the upper switch voltage and the intermediate bus.

The problem with the intermediate bus architecture is that the conditions for both IBC and niPoL to operate efficiently are conflicting. Figure 2 compares several methods for converting a 48V distribution bus to 1V. The width of each distribution bus represents the current it carries.

The first example shows the direct conversion of 48V to 1V using niPoL. Although the current and power consumption are very low, the duty cycle of niPoL is only 2%. Too low a duty cycle will cause problems such as high peak current, large input and output ripple, slow transient response, high noise and low power density.

In the second example, the IBC converts the 48V bus to a 12V intermediate voltage. The duty cycle of the niPoL is 8%, which is not much of an improvement. The current carried by the IBC is four times higher than in the first example. To avoid distribution losses, the cross-sectional area of ​​the bus needs to be increased by 16 times, or the distance between the IBC and the niPoL needs to be shortened.

The remaining two examples show the use of IBC to convert 48V to 3V or 2V. The lower the voltage, the higher the duty cycle. However, the intermediate bus current is also larger, and the distribution loss is greater. Due to the high bus current, in these two examples, the IBC and niPOL have to be very close. In the 2V example, the duty cycle of niPOL is 50%, which is good, but the IBC has to follow the tail of niPOL, and they are so close to each other that they are a whole DC-DC converter, which shows that the separation of the DC-DC converter into two devices cannot be achieved in IBA, repeating the dilemma of distributed architecture and failing to take advantage of IBA.

Another problem with IBA is the transient response of the niPOL. Can the niPOL quickly increase or decrease current in response to load changes? The fundamental difficulty is that it places the inductor in the wrong place.

The rate of change of the current in the inductor is determined by the voltage applied to the inductor. In low voltage applications, when the load is in a high current state, its current change rate is limited by the output voltage. When the output voltage is lower, the current change rate is smaller, and it takes longer to reduce the current, that is, it is more difficult to stop the inertial current of the inductor, and the recovery time is also longer, and a large capacitor needs to be added to the output.

The large capacitor placed in front of the niPOL is responsible for filtering and maintaining low impedance, but it has little effect on load bypass. Due to the improper placement of the inductor, current inertia is generated, so a large capacitor is needed at the output to maintain stability.

In general, there are inherent conflicting effects in the IBA architecture, the root cause of which can be traced back to the basic Ohm's law, and it can only be used within certain ranges. However, for other applications, the above-mentioned shortcomings emerge.

Factorized Power Architecture (FPATM)

The factorized power architecture rearranges the functions of the DC-DC converter and implements them with chip-packaged components. Its main components are the pre-regulator module (PRM) and the voltage conversion module (VTM). The PRM only has the voltage regulation function, while the VTM has the voltage transformation and isolation functions. Together, the PRM and VTM can realize the functions of the DC-DC converter. The PRM can accept a wide input voltage and convert it into a regulated factorized bus (Vf) and transmit it to the VTM. As a point-of-load converter, the VTM steps up or down the factorized bus and provides an isolated voltage to the load. The load change is transmitted to the PRM by the feedback circuit, and the PRM regulates the factorized voltage to achieve voltage regulation.

Unlike distributed architecture or intermediate bus architecture, in the factorized architecture, the voltage regulation function is provided by the PRM, which can be far away from the load. As a load point converter, the VTM does not need to provide voltage regulation and does not need to be close to the load. It is only responsible for "doubling the current" or "reducing the voltage" according to the K ratio (VOUT = Vf ? K). The VTM can transmit current throughout the conversion cycle, and its duty cycle is 100%. FPA transmits power through the factorized bus, and can choose the voltage more arbitrarily, without the IBA architecture mentioned above. Due to inherent conflicts, the intermediate voltage can only be selected at a voltage slightly higher than the load, otherwise its duty cycle will be unmanageable.

Since VTM is responsible for voltage transformation at the load point, its K ratio can be as high as 200. Therefore, the ratio bus is not limited by the load voltage and can be set at any point. The ratio bus can even be set to the same voltage as the power supply. As shown in Figure 5, the load voltage is 1V, and the ratio bus can be set to 48V. It is completely unaffected by the load voltage or the distance between PRM and VTM, and there is no need to make a trade-off between transmission loss and conversion loss. The key point is that FPA puts the voltage transformation part at the load point, overcoming the difficulties faced by IBA, and the duty cycle can reach 100%. FPA has better transient response than IBA. As mentioned above, IBA puts the inductor between the transfer bus and the load to generate current inertia. There is no inductor between the FPA ratio bus and the load (Figure 6). Since VTM is not affected by inductor inertia, it can respond quickly to load changes. The capacitor in the ratio bus can effectively bypass the load because there is no inductor barrier. This capacitor is equivalent to adding 1/K2 times the capacitance value to the load, so there is no need to add a large capacitor at the load point. Figure 7 clearly shows that only 4uF capacitors are needed in FPA to replace the 10000uF capacitor in IBA.

Factorized Power Architecture, the Power Architecture of the Future

Although IBA is still an effective and low-cost solution for low-voltage applications, it has inherent limitations and conflicts in structure. It requires a compromise between transmission loss and conversion loss, and sacrifices transient response.

In contrast, FPA and VI chips do not have these limitations. VI chips are very flexible and efficient components. They can be used in centralized, distributed and transit bus architectures. Engineers can instantly improve system performance, greatly reduce system space, and improve transient, heat dissipation and noise issues. FPA and VI chips will be the model for future power architectures and components.