Analysis and Design of Slope Compensation in Peak Current Mode Boost DC-DC Converter

Switching power supplies can be divided into two categories according to the control mode: voltage mode and current mode. Compared with the voltage mode, the current mode is widely used due to its advantages such as fast dynamic response, simple compensation circuit, large gain bandwidth, and easy parallel output. However, there are the following problems in the peak current mode: open-loop instability of the system when the duty cycle is greater than 50%; open-loop instability of the system due to peak current rather than average inductor current; subharmonic oscillation; poor anti-interference ability, especially when the ripple current component in the inductor is very small, this situation is more serious. The solution to the above problems is simple, that is, to add a slope compensation circuit. This article introduces the basic principle of slope compensation for fixed frequency, peak current mode boost DC-DC converters, and designs a simple and practical slope compensation circuit.

The basic principle of slope compensation
i_sense is to sample the current of the power switch tube, which is equivalent to sampling the inductor current during the ton time. The sampled current i_sense is converted into a voltage signal Vi, which is then input into the PWM comparator and compared with the output Vea of ​​the error amplifier, thereby controlling the on and off of the power switch tube and achieving the function of stabilizing the output voltage. Obviously, the output Vea of ​​the error amplifier determines the peak value of the inductor current, which is assumed to be IRef here.
First, consider the case without slope compensation.

In a cycle from t=nT to t=(n+1)T (T is the switching cycle), the inductor current rises linearly to Iref and then starts to decrease. Let the inductor current at t=nT be in, the inductor current at t=(n+1)T be in+1, the output voltage be v, and the duty cycle be D.

If the small disturbance of the current in is considered in the steady state, according to the boost formula v/Vin=1/(1-D), and the high-order terms of the last two terms in in in formula (2) are ignored, then:

Let l=-D/(1-D), then in order to make the system stable, l must satisfy -1 Now consider the case where a slope compensation current signal with a slope of mc is superimposed on the inductor current, where mc>0. At this time, the equations for the rising and falling inductor current are as follows:

In order to make the system stable, l must satisfy -1 From formula (4), it can be found that superimposing a positive ramp signal (mc) on the inductor current is equivalent to superimposing a negative ramp signal (-mc) on Iref, that is:

When the duty cycle D is constant, if D<0.5, the system can be stable without slope compensation; if D>0.5, to achieve system stability, the compensation slope should satisfy:

Design and implementation of slope compensation circuit
Slope compensation can be implemented by summing a slope current signal i_slope and an inductor current sampling signal i_sense, and then inputting it into an IV circuit to generate Vi, and then comparing it with the output Vea of ​​the error amplifier to set the duty cycle and stabilize the output voltage. The constant current charge and discharge oscillator can obtain a clock pulse signal with a fixed frequency and a fixed duty cycle and a slope voltage signal with a constant slope. The clock pulse signal is used to set the operating frequency and maximum duty cycle of the voltage converter, and can enable the control circuit to effectively implement pulse-by-pulse control of the current mode. The slope voltage signal can be used to generate a slope current signal i_slope for slope compensation.

Oscillator circuit
Among them, MP4~MP8, MN6~MN9 are comparators, which form a Schmitt trigger with inverters INV1, INV2, and INV4, and MP3 and MP2 are current sources. The oscillator circuit requires a reference voltage signal VREF to set the upper and lower threshold voltages of the Schmitt trigger, and the current source IREF is used to generate a constant current for charging and discharging the capacitor C. VREF and IREF can be provided by the reference voltage source and reference current source inside the boost converter system.

Generation of slope compensation signal
Although the voltage on the capacitor C in the oscillator is a ramp signal, voltage summation is not as simple as current summation, so a VI circuit is used to convert the ramp voltage into a ramp current, which makes it easier to achieve slope compensation. The specific implementation circuit is shown in Figure 3.

VL is the lower threshold voltage of the Schmitt trigger; VC is the voltage across the timing capacitor C, VC≥VL. MP11, MP12, and MP15 are a group of mirror current sources with equal current magnitudes. When VC=VL, the currents of MN19, MN20, and MN21 are equal, that is, equal to the current value of the current source. When VC increases, the current on MP14 decreases, and part of the current on MP12 flows to MP13 through R4. MN21 and MN20 are current mirror structures, so the current of MN21 decreases. At this time, i_slope is equal to the current flowing through R4.

Assume that MP11, MP12, and MP15 are fully matched, MP13 and MP14 are fully matched, and MP19, MP20, and MP21 are fully matched. ro is the small signal output resistance of MP14:

When I1 and C are fixed, the rising slope of i_slope can be adjusted by changing the resistance value of R4.

In order to ensure the stable operation of the boost converter, a compensation signal with a certain slope needs to be superimposed on the inductor current, and the requirements of formula (8) must be met. The compensation method of this circuit is to input i_slope and i_sense together into a summing circuit for superposition, so the i_slope slope should meet:
Simulation results and analysis
In the 0.8mm BiCMOS process, Hspice is used to simulate the oscillator circuit and the slope compensation circuit.

The oscillator clock pulse CLK output waveform, the slope voltage signal VC waveform, and the slope compensation signal i_slope output waveform, where VDDA is 3V, VSSA is 0V, IREF is 0.5mA, and VREF is 1.24V, and the oscillator frequency is 622kHz.

Conclusion
This paper analyzes the slope compensation principle in the peak current mode boost DC-DC converter and proposes a simple and practical slope compensation circuit. The simulation results show that as long as the value of the resistor R4 in the VI circuit is reasonably adjusted, the slope compensation amount that ensures the stability of the system can be obtained. ■