Solution for balancing input ripple current using programmable power supplies

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In this article, we will explore how to use programmable power supplies and phase shifting to reduce the stress on the input capacitors while retaining the benefits of synchronization. (Synchronizing the switching frequency of the on-board buck converters is necessary to easily control EMI and block unwanted beat frequencies. However, synchronizing every buck converter on the board has an undesirable consequence. This puts considerable stress on the input capacitors.)

Before we look at the solution, let's analyze the problem in detail. When the input power supply of the system mainly delivers DC current, the various input capacitors of the buck converter will deliver discontinuous pulse current. The design of this pulse current basically takes into account the required ripple and RMS current of each converter. That's simple. The unexpected thing happens when there are multiple converters on the board. No converter will take the reverse current exactly from the capacitor designed as its input capacitor. Undoubtedly, most of it comes from the nearest low impedance source, but in reality, the switching stage will also draw the necessary current from the entire capacitor network on the board. In a fully synchronous system, the sum of all converter pulse currents will be drawn at the same time. Therefore, the RMS current obtained by a single capacitor will be formed. This makes sense because the power dissipation of the capacitor in the ESR is proportional to the square of the RMS current. This will have the unexpected effect of stressing all capacitors multiplying, which will reduce reliability. In addition, this will increase the peak value of the conducted emission surface.

Phase shifting is a simple solution. This approach is to delay the edge of the clock pulse for each converter so that it arrives at the appropriate time within the original clock period. If done correctly, this will minimize the amount of pulse current overlap in the input capacitors. Therefore, the RMS current in each capacitor will be reduced appropriately, and the peak value of the conducted emission surface will also be reduced.

In the past, phase-shifting synchronous clocks could be accomplished using analog circuits or FPGAs. Unfortunately, this adds extra components, cost, and development effort. Fortunately, there are several digital PWM controllers on the market today that integrate synchronization and phase shifting. In this article, Exar’s PowerXR technology demonstrates the benefits of phase shifting, as shown in Figure 1.

Figure 2 shows the distributed acquisition of the input pulsed current. In this example, only one channel is running on the PowerXR evaluation board. This channel performs a 12V to 1V conversion with an 11A load. The waveform shows the current through the inductor and the current in all four input capacitor banks. This scope capture shows how the power stage integrates the pulsed current from the entire capacitor network to acquire the inductor during the switch "on" time. Channel 2 in blue toggles the clock output on a GPIO pin of the PowerXR controller. In this case it is used for convenient triggering, but it can be used to further synchronize the PWM controller.

We will now demonstrate the action of a fully loaded power system on the input capacitor of a single buck converter. For this demonstration, the PowerXR controller was reconfigured to represent a typical high power embedded design by providing the following outputs from a 12V input:

? Channel 1 - 1.8V (at 3.5A)

? Channel 2 - 1.2V (at 9.4A)

? Channel 3 - 2.5V (at 4.9A)

? Channel 4 - 1.0V (at 11.4A)

Figure 3 shows a scope picture covering the inductor current in all four switching phases and the pulse current of the decoupling channel 1 input capacitor.

Note in particular that the peak is close to 5A and the RMS current through the capacitor is measured at 1.26A. If the current through the capacitor was only to meet the needs of Channel 1, then according to the following equation it would only be about 1.6A peak and the RMS current would be much lower (assuming about 90% efficiency). This is clearly not the case and deserves the attention of the system designer.

Figure 4 shows the same test case with one change. The PowerXR controller is instructed to place the switching stages 90 degrees out of phase. This is most clearly shown in the inductor current waveform.

Note how the current pulses through the input capacitor of channel 1 now occur at a higher frequency and are significantly reduced in amplitude. As a result of this positive change in events, the RMS current through the capacitor is reduced to 885mA. This is a 50% reduction in ESR power dissipation compared to 1.26A in the non-phase-shifted approach.

These results demonstrate that phase shifting is a clear advantage for clock synchronization of multiple switching regulators on a single board. Implementing this technique provides several new options for power supply designers. Component count is reduced by maximizing the work performed by each capacitor and minimizing the stress it experiences. Reliability of a particular design is improved due to the reduced stress on the input capacitors. The reduced pulse current amplitude per stage and the increased effective pulse frequency result in simplified EMI designs.

Reference address:Solution for balancing input ripple current using programmable power supplies

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