Research on methods of reducing power consumption in embedded systems

introduction

With the rapid development of embedded system applications, portable devices such as PDAs and mobile phones have penetrated into every corner of production and life, and the embedded system market has a rapid growth trend. Embedded systems are generally powered by batteries, and most embedded devices are constrained by size and weight. Reducing power consumption can not only extend battery life and shorten the battery replacement cycle for users, but also improve system performance and reduce system overhead, and even protect the environment.

1 Power consumption analysis of embedded systems
To study the low-power design technology of microprocessors, we must first understand the sources of its power consumption. As shown in Figure 1, the conclusions drawn from high-level simulations show the power distribution relationship of high-performance CPUs obtained through switch-level power simulation. Among them, clock power consumption accounts for the largest proportion, including clock generation, drivers, clock trees, latches, and all clock-loaded devices; the power consumption of the data path is second only to the clock, mainly including the execution unit, bus, and register file; the power consumption of on-chip memory is mainly determined by the size of the memory and the circuit and physical structure of the memory array; the power consumption of the control unit and I/O usually accounts for a small part of the total chip power consumption.

2 Low-power design of embedded systems
Low-power design is a complex and comprehensive topic. In terms of process, it includes power modeling, evaluation, and optimization; in terms of design abstraction level, it includes all abstraction levels from the hardware bottom layer to the application layer. Currently, low-power design is mostly implemented at the operating system layer, as shown in Figure 2. At the same time, power optimization is closely related to the optimization of indicators such as system speed and area, and a compromise needs to be considered. The following discusses the commonly used low-power design technologies and specific applications based on the different levels of each part in the embedded system.

2．1 低功耗硬件设计
低功耗硬件设计是嵌入式系统降低功耗的重要内容。因此，需要从系统内部结构设计、系统时钟设计和低功耗模式等几方面采用特定的方法(例如，门控时钟和可变频率时钟、并行结构与流水线技术、低功耗单元库、低功耗状态机编码、Cache低功耗设计等)来实现系统硬件节能设计。下面介绍门控时钟和可变频率时钟的应用。时钟是惟一在所有时间都充放电的信号，而且很多情况下引起不必要的门的翻转，因此降低时钟的开关活动性将对降低整个系统的功耗产生很大的影响。门控时钟包括门控逻辑模块时钟和门控寄存器时钟。门控逻辑模块时钟对时钟网络进行划分，如果在当前的时钟周期内，系统没有用到某些逻辑模块，则暂时切断这些模块的时钟信号，从而显著降低开关功耗。图3为采用“与”门实现的时钟控制电路。门控寄存器时钟的原理是当寄存器保持数据时，关闭寄存器时钟，以降低功耗。门控时钟易引起毛刺，必须对信号的时序加以严格限制，并对其进行仔细的时序验证。

Another commonly used clock technology is variable frequency clock. It can configure the appropriate clock frequency according to the system performance requirements to avoid unnecessary power consumption. Gated clock is actually an extreme case of variable frequency clock (that is, there are only two values ​​​​of 0 and the highest frequency). Therefore, variable frequency clock is more effective than gated clock technology, but it requires the system to embed the clock generation module PLL, which increases the design complexity. Figure 4 shows the clock system design scheme on an embedded chip with low power consumption characteristics. The on-chip clock system stabilizes the 16 MHz input clock through two digital phase-locked loops CPUPLL and SysPLL, and sends them to different multipliers and dividers respectively. The clock signal through CPU-PLL is used as the processor core clock, and the clock signal through SysPLL is used as the system clock, memory clock and peripheral clock outside the processor core.
Since the processor chip (such as i.MX1) does not support dynamic voltage adjustment, the core frequency can be dynamically adjusted by configuring the on-chip digital phase-locked loop. Calculate the system frequency according to the formula:

Among them: fref is the low-frequency clock frequency of the system, which serves as the reference frequency for frequency multiplication; MFI is the integer part of the frequency multiplication factor; MFN and MFD are the numerator and denominator of the frequency multiplication factor respectively; PD is the preset frequency division factor.
2.2 Operating system layer
System-level low-power design is generally implemented at the operating system layer. Because the operating system manages all software and hardware resources of the system, obtains various status information of the system, and controls the status of hardware devices. Therefore, it is the best choice to implement global power consumption control in the operating system. The operating system level is divided into a power consumption driver module and a power consumption scheduling module.
2.2.1 Power consumption driver module
The driver module is relatively simple to implement, mainly for hardware operations. Power consumption mode conversion and frequency adjustment are both set through the on-chip clock system control register. Therefore, it is essentially a register setting. It is relatively easy to enter the running mode from sleep mode or stop mode. You only need to send an interrupt signal to the system to wake up the system and enter the running mode. However, it is relatively complex to go from running mode to sleep mode or stop mode. The key code is as follows:

2.2.2 Power Scheduling Module
The key technologies for implementing the power scheduling module are specifically reflected in the embedded Linux operating system. In the Linux operating system, the scheduling of tasks is mainly completed by the process scheduling (or task scheduling) module schedule(). schedule() grasps the running status of all processes in the system and manages and schedules their execution priorities. Therefore, to achieve power consumption control at the system level, it is necessary to fully rewrite the schedule() module of the embedded Linux kernel and add DPM and DVS strategies to it. The design idea is: since the cpu_usage_stat structure provided by the Linux kernel records the distribution of the processor running time, the current system operation ratio can be calculated by reading these parameters, that is, the specific operation is implemented through the cpu_scan function. The cpu_scan function is the main part of the processor device driver. It is called within a fixed time slice. The size of the time slice can be selected between 5 and 1D0 ms as needed. This function evaluates the system status by calling the cpu_dvs function and the cpu_dmp function. These two functions are the implementation of variable voltage technology and dynamic power management respectively.
(1) DPM strategy
The DPM strategy is divided into two parts: observer and controller in the implementation of low-power embedded Linux system, as shown in Figure 5. We used the Timeout algorithm in the implementation process. The algorithm is simple to implement and has high prediction accuracy. Statistics show that as long as the Timeout is designed reasonably, the credibility of this assumption is 95%. The cpu_dmp function that uses the Timeout algorithm will not be explained in detail here. However, in the implementation of dynamic power management, it is easy for a wake-up signal to be sent to a process in the waiting queue, and the process cannot be scheduled for execution immediately, resulting in event loss. In order to avoid this situation, Llow is set to a value slightly smaller than Lmax. When the number of events reaches Llow, even if the event processing process cannot be executed immediately after being awakened, due to Llow

The code for updating the event list algorithm is as follows:

Explicit resources require some modifications to the driver, that is, inserting a NotifyEvent() function call at two time points: before the driver sends an execution command and after the hardware completes the service and tells the kernel through the driver that the device is ready. The specific code insertion point varies according to different types of devices and different definitions of the start and end of the service.
After calculating the optimization strategy based on the system resource access history obtained by the observer, the control module will insert a NotifyEvent() function call at two time points: sending a control command to the corresponding hardware through the power management machine to complete the service and after the driver tells the kernel that the device is ready.
(2) DVS strategy
At present, embedded systems often use dynamic voltage scaling technology III to reduce power consumption, that is, the operating frequency of the processor can be controlled by setting a programmable frequency register when the system is running. Experimental observations have found that the operating load of the system has obvious non-stationary characteristics. It may have a high execution load in a short period of time, but it maintains a light load state most of the time. Based on this characteristic of embedded systems, DVS technology sets the processor to the highest execution speed when the system load is heavy to ensure the computing power of the system; and dynamically reduces the processor's operating frequency when the system load is light to reduce the processor's execution power consumption, thereby achieving optimal control of the system's computing performance and power consumption, as shown in Figure 6. DVS prediction is implemented by the cpu_dvs function which uses the time interval AVGn algorithm. This function reads the CPU usage information, estimates the system load according to the AVGn algorithm, and implements specific dynamic voltage scaling based on the result returned to the cpu_scan function.

The AVGn algorithm analyzes a variety of simple or complex estimation algorithms and smoothing techniques. The basic idea is to use the exponential smoothing average method, that is, to predict the weighted average of n running percentages of the upcoming interval. However, there is a problem with the AVGn algorithm, that is, the frequency change step by step causes the system to not respond to load changes in a timely manner, and a lot of in-depth and detailed research is needed.
2.3 Application layer
In systems based on microprocessors and microcontrollers, software plays a leading role in guiding hardware activities. In other words, software has a great impact on the energy consumption of the system. Until now, there is no effective and accurate method to evaluate the effect of software design on energy consumption. Without energy evaluation, it is impossible to optimize the software and reduce power consumption. Among the many factors that cause CPU power consumption, at least two are greatly affected by software-the storage system and the system bus. In the low-power software design of embedded systems, these two factors are mainly considered.

3 Summary
Power consumption has become a priority issue in embedded system design. As processor speeds get faster and faster, how to reduce power consumption has become an important aspect of measuring the performance of embedded systems. Therefore, in the design of low-power embedded systems, it is necessary to consider the specific low-power design methods of each part, and at the same time, give full play to the low-power technology advantages of each abstract layer.
There are still many deficiencies in the low-power embedded system introduced in this article, which need further exploration: ① The DPM random decision model and solution algorithm do not answer basic questions such as whether the optimal strategy exists and what characteristics the optimal strategy has if it exists, and they cannot explain theoretically why "the timeout strategy can achieve excellent energy-saving effects in practice". ② The DVS strategy in this article adopts assumptions similar to those of the AVGn algorithm, which are too harsh in practical applications. How to apply the ideas of the DVS strategy in this article to specific embedded systems with non-ideal conditions requires further research.