Interleaving Power Stages—Not Just for Buck Converters Anymore

introduction

For the voltage regulator modules (VRMs) that power the latest computer central processing units (CPUs), power supply designers have historically used multiphase interleaved buck converters. These VRMs have been carefully designed to meet the stringent regulation and transient requirements of Pentium4 and Athalon CPUs. Interleaved buck converters are ideal for low voltage, high current applications because they reduce input capacitor RMS current and output capacitor ripple current compared to standard buck converters, and the output capacitor bank is smaller. Designers can also benefit from interleaving two buck converters in the same way as they do with two forward converters. In high current applications such as intermediate bus or commercial power supplies, using interleaved forward converters may be more advantageous than using a standard forward converter topology.

Conventional forward converter

The input current of the forward converter is discontinuous and should be filtered by the input capacitor (Cin). This results in a high input capacitor RMS current (Icin).

The output filter inductor (L1) is sized with an inductor ripple current (ΔIL1) of approximately 25% to 30% based on the output current (Iout) to meet the output ripple voltage requirement (Vripple).

The output capacitor (Cout) can be sized to suppress the inductor ripple current to meet the output voltage ripple requirement. The following equation can be used to estimate the maximum equivalent series resistance (ESR) and minimum output capacitance (Cout). Under normal circumstances, the capacitor selection is mainly determined by the ESR requirement, which requires a higher capacitance to suppress the inductor ripple current.

Advantages of Interleaved Dual Forward Converters

An interleaved forward converter is simply two forward converters operating 180 degrees out of phase, with the advantage of reducing the input capacitor RMS current and the output capacitor ripple current.

The input current of each forward converter is intermittent (i.e., It1 and It2). The input current of the interleaved converter is the sum of the two intermittent input currents. Due to the 180-degree phase difference, the input current is more continuous and close to DC. After the two converters are interleaved, the input capacitor (Cin) only needs to filter the AC part of the input current, so it can be greatly reduced. Figure 3 shows the reduction in RMS current.

The output current (Iout) of the interleaved converter above is the sum of the two inductor (I1 + I2) currents minus the capacitor current (Icout). The output capacitor (Cout) in this application must also suppress the AC portion of the output filter inductor. However, because the two converters operate 180 degrees out of phase, the inductor ripple currents cancel each other, which produces a more continuous output current and reduces the amount of ripple current that Cout must suppress. The output capacitor size is similar to the forward converter and should meet the output ripple voltage requirements. However, the output capacitor does not have to suppress the entire inductor ripple current. This allows the output capacitor to have a larger ESR.

Theoretically, the output inductor ripple current cancellation characteristic of this topology allows the designer to reduce the size of the filter inductor. However, to reduce overall losses in high current applications [1], the inductor should generally remain the same size, if not larger.

At 50% duty cycle (D) the capacitor ripple current reduction is optimal

It is important for designers to understand that the largest reduction in capacitor current occurs at 50% duty cycle. Figure 4 shows the waveforms of the input and output capacitor currents at approximately 40% duty cycle. Since the duty cycle is less than 50%, the input current of the interleaved converter is less continuous, which also increases the RMS current of the input capacitors. The output inductor ripple current is no longer symmetrical and does not cancel when the converter operates at 50% duty cycle. This increases the amount of capacitor output ripple current.

The following equation and the graph in Figure 5 show how the capacitor RMS current (Icin(RMS)) varies with duty cycle, where N is the transformer turns ratio. We can observe that the lowest input capacitor RMS current occurs at 50% duty cycle, while the highest RMS current occurs at 25% and 75% duty cycle.

- Input capacitor RMS current when D ≤ 0.5

- Input capacitor RMS current when D > 0.5

The following equation and graph show how the ratio of output capacitor ripple current (ΔIcout) to inductor current change (ΔIL) changes with duty cycle. Figure 6 shows that the maximum inductor ripple current cancellation occurs at a 50% duty cycle.

Design Considerations

To achieve the maximum reduction in filter capacitor current when doing an interleaved forward design, the correct choice should be made over the duty cycle range. This can be achieved by adjusting the transformer turns ratio (N) based on the input and output voltage requirements of the specific design.

The following equation can be used to estimate N, where Vin(min) is the minimum input voltage and Dmax is the selected maximum duty cycle. Vd represents the forward voltage drop of the output diode.

Once the maximum duty cycle and transformer turns ratio are determined, the minimum duty cycle (Dmin) can be calculated. Using the information and plots in Figures 5 and 6, we can derive the worst-case filter capacitor current for this design.

Design Examples

A dual interleaved forward converter was built using the UCC28221 interleaved PWM controller to show how much the capacitor ripple current varies with duty cycle. The 200W converter was designed for an input voltage range of 36V to 76V with a 12V regulated DC output. A two-to-one change in input voltage will cause a duty cycle change of approximately two-to-one. A maximum duty cycle of 0.6 was chosen for the design to optimize transformer reset and reduce capacitor current. Each converter was designed for a switching frequency (fs) of 500 kHz to suppress magnetic strength. The output diodes of this design are Schottky diodes with a Vd of approximately 0.3V. This results in an N of 1.75 to 1 and a minimum duty cycle of 0.28.

To suppress the peak input current of the forward converter, the output inductor is carefully designed for a ripple current of 60%. This makes the filter inductor about 3.5uH, which is basically the same as used in a single forward converter where the inductor ripple current is about 30% of the maximum load current (Iout).

The output capacitor ripple specification for the above design is 200mV (Vripple) maximum. The output capacitor ripple current is maximum when the power converter operates at 0.28, the minimum duty cycle. The output capacitor should suppress the ripple current to meet the output ripple requirement. The graph in Figure 6 shows that the output capacitor ripple current is about 60% of the filter inductor ripple current. This makes the capacitor ripple current about 3A (ΔIcout). This design requires an ESR less than 66mΩ to meet the output voltage requirement.

The maximum allowable ESR for a forward converter design with the same switching frequency and power level is about 40mΩ. Interleaving converters allows designers to use 1.7 times more maximum allowable ESR than the standard topology for this design. But the exact results will vary with the design requirements. If the minimum duty cycle of the converter design is 0.4, then the maximum allowable ESR designed for the same power level and output ripple requirements will be 120mΩ. This is about three times the allowable ESR of a standard forward converter.

The output capacitor RMS current (Icout(RMS)) of this design is approximately 1.74A, which is approximately 60% of that of a standard forward converter.

For this design, the input capacitor RMS current is maximum at a duty cycle (D) of approximately 28%. The maximum input capacitor RMS current is approximately 2.4A. A conventional forward converter with a similar power stage design has an input capacitor RMS current of approximately 4.7A. For this design, using interleaved converters will reduce the input capacitor RMS current by approximately 50%.

The following oscilloscope waveforms show how the ripple current cancellation varies with duty cycle. Figure 7 reflects the operation of the power converter at 50% duty cycle. The sum of the two output inductor currents (IL1+IL2) is almost DC, which makes the output capacitor ripple current almost zero.

The oscilloscope waveform in Figure 8 shows the converter operating at maximum line voltage (about 76V). Proper regulation of the 12V output requires a duty cycle of about 28%. From the oscilloscope waveform, we can observe that the sum of the inductor currents has a peak-to-peak ripple current of 3A, which should be filtered by the output capacitor. This peak-to-peak capacitor ripple current (ΔIcout) is about 60% of the inductor ripple current.

in conclusion

Dual interleaved forward converters can be beneficial for high current/high power density designs. This converter topology is ideal for intermediate bus converters and commercial power applications because the reduction in input and output capacitor ripple current reduces the stress on the input and output capacitors. The inductor ripple current cancellation of the interleaved converter allows the design to achieve a higher output capacitor ESR, which in turn allows us to reduce the output capacitor requirements of the design.

References:

[1] Sophie Chen, "Using the TPS40090EVM-001, User's Guide", Texas Instruments (TI) literature number SLUU175, page 9

[2] Brian Shafer, "Interleaving provides unique advantages for forward and flyback converters," TI Power Design Seminar 4, SEM 1600