Non-Synchronous Buck Regulator Designed for Light Load Operation

Typically, buck regulators are designed for continuous mode operation, which simplifies output voltage calculations and system design. However, if the system is non-synchronous and required to operate under light load conditions, the situation becomes more complicated. Under these conditions, the buck regulator may switch to discontinuous mode operation. The duty cycle changes from the ratio of output voltage to input voltage (Vout/Vin) to a complex function involving inductor value, input voltage, switching frequency, and output current.

Normal operation

Figure 1 shows the floating gate driver output driver stage of the buck controller of the buck regulator when the system is powered on. The reference voltage Vref (this separate supply is used to improve energy efficiency) supplies the NFET gate driver until the diode voltage drops below the reference voltage, allowing the driver to fully operate. There is enough voltage to drive the gate (G) of the FET because the initial condition dictates that the output is 0V, so the source (S) voltage of the FET (Q1) is also 0V.

Figure 1. Buck regulator during power-up.

Flyback

Sufficient load allows the system to operate properly in continuous mode. During the flyback event caused by the FET turning off (see Figure 2), there is always current flowing through the external FET or D2 to the inductor. The flyback event produces a voltage at the source of Q1 that is limited by the voltage drop of D2. There will be a negative voltage with respect to ground. Also, because the switching of the boost capacitor (Cboost) increases the gate voltage, there is enough voltage to drive Q1; the boost capacitor provides a high voltage back to the boost (Boost) pin and a corresponding negative voltage to the source (S) of Q1.

Figure 2. Flyback condition.

transition

During light load conditions where the average current demand is less than half of the current ripple, the system will enter discontinuous mode. This is caused by the condition of driving the output current which is reverse limited by the diode (D2). The output is likely to overshoot (due to the slow response time of the control loop) and hang at the overshoot position, and the operation is generally somewhat unpredictable, missing pulses due to lack of demand due to higher voltages.

The Problem

But there are more issues to consider in the circuit setup we are looking at. After Q1 turns off, the boost capacitor (Cboost) begins to discharge (Iboost) through the BOOST pin, providing current to any support circuitry and leakage current (Ileakage) through D1, as shown in Figure 3. The extended off time of Q1 in discontinuous mode begins to discharge the charge accumulated in the boost capacitor, allowing the charge to drop far enough to drop to a critical level. Once the critical level is exceeded, it prevents the Q1 FET from turning on (which may vary from component to component, but is typically around 3V on the boost capacitor voltage). The source of the FET is maintained at approximately its regulated voltage (8V in Figure 3, depending on the voltage at which the boost capacitor is turned on).

Q1 will not turn on until the output capacitor is sufficiently discharged and provides a sufficiently low voltage to the source of Q1 relative to the boost pin voltage (6V-D1) through D1.

Figure 3. Boost capacitor discharge.

in conclusion

Designers should carefully evaluate the switching power supply design under all load conditions. Considerations include over temperature. High temperatures will create an environment with higher leakage currents. The temperature coefficient of the current flowing into the boost pin is unknown, so designers need to check low temperature conditions as well. This result should also be used in the worst-case evaluation simulation process to complete the system evaluation and determine the minimum capacitor value. Careful design can also add engineering buffers to the calculations.

The solutions to the issues discussed in this article include:

1. Increase the boost capacitor (Cboost) value to eliminate low voltage discharge events.

2. Move to components that use ground referenced gate drivers.

3. Modify the design so that it works synchronously.

4. Change the reference voltage connected to D1 (increase the voltage).

5. Replace D1 with a low leakage Schottky diode.