Behavioral Simulation of Pipeline ADC

Analog-to-digital converter (A/D converter) is a basic circuit widely used in various electronic systems. Its performance ultimately affects the performance of the designed system. A high-resolution, fast conversion speed, and superior performance analog-to-digital converter has always been the most challenging design task in integrated circuit design. Since the key part of ADC is analog, its design depends largely on circuit simulation, but it takes a lot of time to simulate ADC at the transistor level using common circuit simulation tools. For this reason, people adopt the idea of ​​hierarchical design of digital integrated circuits and propose a method of first establishing a behavioral model for behavioral level simulation optimization and then performing specific circuit design at the circuit level to shorten the overall design time. Tools and languages ​​such as MATLAB/Simulink, VHDL-AMS, and Verilog-AMS and corresponding simulation software provide a means to realize the behavioral simulation of such analog-digital hybrid circuit systems.

The key to behavioral level simulation is the accuracy of the simulation, which mainly depends on the accuracy of the behavioral model of each unit circuit. In previous literature, the model used for each unit circuit is generally composed of adding some links reflecting the common non-ideal characteristics of the circuit to the basic functional model. The nonlinear effect or high-order dynamic effect of the circuit is not considered enough, and the working characteristics of the circuit cannot be fully reflected, so the accuracy is limited. One of the main unit circuits in the pipeline ADC is the operational amplifier. The sample-and-hold circuit and MDAC are mainly composed of operational amplifiers. The comparator is basically equivalent to an open-loop operational amplifier. Therefore, the accuracy of the operational amplifier model basically determines the accuracy of the entire ADC behavioral simulation. This paper adopts a model constructed based on circuit macro model technology for the operational amplifier, and constructs the model of the sample-and-hold, MDAC and comparator circuit based on this model, so as to ensure that the behavioral level simulation obtained in this way has high accuracy.

The following first introduces the operational amplifier model used in this paper, then introduces the structure of a 7-bit pipeline ADC and its behavioral level model, and then gives the results of the behavioral simulation and the comparison with the circuit level simulation results. From the results, it can be seen that the simulation using the behavioral model of this paper can obtain high-precision simulation results, and the simulation time consumed is greatly shortened.

1 Operational amplifier model

In high-level simulation of analog or analog-digital mixed signal circuits, the operational amplifier is usually equivalent to a linear model based on a controlled power supply, plus consideration of non-ideal factors such as limited gain bandwidth, slew rate, and output resistance. Although such a model includes some important non-ideal effects of the operational amplifier, it does not consider the nonlinearity of the operational amplifier, nor the high-order dynamic effects of the operational amplifier. When the operational amplifier operates at a high speed or enters the nonlinear region at low voltage, it may cause more obvious errors. In fact, the accurate analysis of the settling time of a closed-loop operational amplifier under the action of a step signal must consider both nonlinear and linear operating ranges. Therefore, it is necessary to use a more comprehensive operational amplifier model in the behavioral simulation of circuits such as ADCs.

This article uses an operational amplifier model constructed based on circuit macro model technology. This model is obtained by simplifying the specific structure of the operational amplifier circuit. It was originally designed for bipolar operational amplifiers and later extended to MOS operational amplifiers. It also includes input stages, intermediate stages, and output stages, and can reproduce almost all characteristic indicators of the operational amplifier. The input stage is composed of a pair of differential pairs, which can simulate the offset voltage/current and common mode characteristics of the op amp. The intermediate stage and output stage are mainly composed of controlled sources, resistors and capacitors, which simulate the gain, frequency and output characteristics of the op amp. The output stage also includes several diodes to reflect the limiting and current limiting characteristics of the op amp.

Since the nonlinear characteristics of components can be directly described in the form of PWL in simulators such as Hspice, we have simplified the above model. The input stage differential pair in the original model is represented by a nonlinear controlled source and merged with the intermediate stage. The output stage with diode limiting is equivalent to a linear controlled source. The resulting model is shown in Figure 1. Among them, Vin is the input differential mode voltage, Cc is the compensation capacitor of the secondary op amp, I0 and I1 correspond to the nonlinear voltage-controlled current source and the linear voltage-controlled current source respectively, R2 is the output resistor, and capacitor C1 is used to establish the phase margin. This model not only reflects the common non-ideal characteristics of op amps such as gain, bandwidth, and output resistance, but also includes the nonlinearity and second-order dynamic effects of the amplifier.

2 Behavioral model of pipeline ADC
The structure of pipeline ADC discussed in this paper is shown in Figure 2, which consists of a sample-and-hold circuit (S/H), a sub-analog-to-digital converter circuit, a digital-to-analog converter circuit, and an MDAC. Each stage outputs 1.5 bits of digital bits, which pass through a digital correction circuit (0.5 bits of which are used for digital correction). Finally, each stage actually outputs only 1 bit of effective bits. The behavioral models of each part are introduced below.

1) Sample and
hold circuit The basic circuit diagram of the sample and hold circuit is shown in Figure 3. It mainly consists of switches, capacitors and operational amplifiers. By replacing the operational amplifier in the circuit with the operational amplifier model in Figure 1, the behavioral model of the sample and hold circuit is obtained.

2) Comparator
The sub-analog-to-digital converter of the pipeline ADC is a parallel analog-to-digital conversion module composed of several comparators. These comparators use relatively high-speed comparators, which are generally composed of one or more pre-amplifiers and a latch comparator. The offset voltage of the latch can be reduced by the gain of the pre-amplifier, and the input of the latch can be quickly established. Figure 4 is a model of the comparator, which mainly consists of a nonlinear voltage-controlled current source, an equivalent output resistor and a capacitor. The nonlinear voltage-controlled current source is similar to Figure 1, and the resistor R and the capacitor C mainly simulate the output voltage and response time of the comparator.

3) MDAC
is similar to the previous sample-and-hold circuit. The MDAC circuit also uses a switched capacitor circuit, which is mainly composed of an op amp, a switch, and a capacitor. The MDAC circuit mainly realizes the residual amplification function, and its circuit is shown in Figure 5 (here refers to 1.5 bits/level):

When K1 is closed and K2 is open, the circuit is in the sampling stage. Conversely, when K1 is open and K2 is closed, the circuit is in the residual amplification stage. Under ideal conditions, the charge conservation theorem shows that:

where is the sum of all capacitors connected to the reference voltage. When the capacitors are equal, the above equation shows that the output is equal to the sum and difference of 2 times the input and the reference voltage, thus realizing the residual amplification function.
Since both the MDAC circuit and the sample-and-hold circuit use switched capacitor circuits, the established models are similar, mainly modeling the op amp. The modeling mode can be shown in Figure 1.
3 Simulation results
In order to verify the accuracy of the above ADC behavioral model, Hspice was used to simulate a 7-bit pipeline ADC circuit with a sampling rate of 17 MHz at the behavioral level and circuit level. A sinusoidal signal with an amplitude of 1 V and a frequency of 1 MHz was added to the ADC input. Figure 6 is the output of the sample-and-hold circuit in 1/4 cycle. It can be seen that the output waveform of the behavioral level simulation is very close to the output of the circuit level simulation. Figure 7 is a signal spectrum diagram obtained by Fourier transforming the final digital signal (the left figure is the circuit output, and the right figure is the model output). Table 1 shows the ADC performance indicators calculated based on the signal spectrum. It can be seen that the results of the behavioral level simulation are also very close to the circuit level results, indicating that the behavioral simulation model used in this article has high accuracy.

4 Conclusion

Behavioral modeling and simulation play a very important role in the design of analog-to-digital converter circuits. This paper analyzes the various modules of the pipeline ADC, establishes a behavioral model for its main modules, and obtains simulation results through circuit and model simulation. From the results, it can be seen that the model designed in this paper has a high degree of accuracy, thus achieving the purpose of this study.