Introduction to the principle and application of field and zone storage technology

1 Introduction

LED video display screens have the advantages of high brightness, wide viewing angle, long life, high cost performance, and the ability to display various texts, graphics, and images synchronously with computers, play TV, video, DVD and other video signals in real time, and input and edit various multimedia data instantly. Therefore, they are widely used in many public places such as streets, squares, commercial centers, sports venues, entertainment venues, and control centers. However, due to technical problems, extra-large video display screens still face severe challenges, mainly manifested in low grayscale, serious brightness loss, and low refresh rate. In addition, the video signal source of this article comes from the DVI (Digital Video InterFace) interface. The DVI interface outputs digital video signals with a large amount of information. Generally, the video signal is first cached by an external RAM (Random Array Memory) and then processed by the processor. There are many types of external memories that can be used for digital image storage, such as SRAM, DRAM, and SDRAM, and their capacity and speed vary. DRAM and SDRAM are dynamic memories with large capacity and need to be refreshed during use. When the processor does not have an external dynamic RAM interface, a refresh circuit needs to be designed, which brings inconvenience to the system application; SRAM does not need to be refreshed, does not require a dedicated interface, has good real-time performance, and can perform jump addressing, so this article uses SRAM as an external cache memory. The use of field partition storage technology greatly improves the refresh frequency, and the image display effect is clear and stable. A video display system with a resolution of 800×256, a refresh frequency of 90 Hz, and a grayscale of 256×256×256 for red, green, and blue colors is realized. At the same time, the brightness and grayscale are conveniently adjustable with little brightness loss by using this technology.

2 System composition

The overall block diagram of the LED video display system is shown in Figure 1: The system consists of two parts: the sending part and the receiving part. The function of the sending part is mainly to encode and decode the video signal transmitted by the DVI interface to form 24b true color video data and dot clock (CLK), line synchronization signal (HS), field synchronization signal (VS), data valid signal (DE) and other control signals, which are transmitted to the receiving card through the LVDS (Low Voltage Differential Signaling) level. After the data processing of the receiving card, it is transmitted to the Yun LED large screen with a specific drive structure (1/8 scanning mode, 74HC595 drive chip). The focus of this article is to introduce the data processing module of the receiving card.

3 Data Processing

The data processing flow is shown in Figure 2: The receiving card receives the video signal (control signal and data signal) transmitted by the sending card, separates the data in the video signal by bit plane, stores it in the external cache by field, and then reads it out by partition and transmits it to the display driver screen. The bit plane separation module recombines the same-weighted bits of different data into new data and stores it in the memory. The external cache uses two SRAM ping-pong cache technologies to realize pipeline processing of data. The principles and implementations of the bit plane separation module and field partition storage are introduced below.

3.1 Plane Separation Module

The grayscale control method adopted by the video display screen is a combination of field superposition and duty cycle, as shown in Table 1: Field superposition refers to the use of constant frequency scanning of different fields to achieve different grayscale levels, such as D7~D4 in Table 1; Duty cycle control refers to controlling the duty cycle of the lighting time and the off time to achieve grayscale adjustment, such as D3~D0 in Table 1. The premise of these two methods is to achieve bit plane separation of video data. Bit plane separation is implemented by FPGA, which includes two major modules, data shift register and data selector. The principle block diagram implemented by VHDL is shown in Figure 3, where r0-7, g0-7, and b0-7 are the red, green and blue colors of true color image data, respectively, occupying one byte. These 24-bit data lines are stored through an 8-bit wide data shift register, and then output to the external buffer through a color bit selector. Bit plane separation is achieved by controlling the address of the buffer. The data width of the external buffer is 24 bits, so that the three colors of RGB are separated in parallel. The shift register uses pipeline technology to shift in the same-weighted bit of the ninth data while latching and outputting the first eight data bits of equal weight, thus improving the efficiency of data processing.

3.2 Field and zone storage

After the data is separated by the bit plane, the same weight bits of different data form new data. By controlling the address of the memory, the same weight bits of all data in a frame are written in the same segment of the memory, so the write address generator has high requirements. The system requires 256 levels of grayscale, so the memory is divided into 8 segments, and each segment stores bits (fields) representing the same weight value. Among them, 8 segments are replaced by 3 (23) address lines. The large screen with a resolution of 800*256 has 256 rows and 800 columns, so the row address is represented by 8 (28) address lines. The first 5 bits of these 8 address lines are the area address (32 areas), and the last 3 bits are the row address of a area (1/8 scan). The column address is represented by 7 (27) address lines. Because the memory is 24 bits wide, one storage unit represents the same weight bits of 8 RGB points of the LED display screen. The order of priority from high to low is: field address> column address> row address. The three counters are cascaded to form the write address of the memory, and the connection method is: field address (A17-A15), area address (A14-A10), row address in the area (A9-A7), column address (A6-A0). It can be seen that field (8 fields) storage can be achieved by changing the priority of the memory address line.

Data is written into the memory in 8 fields, and is required to be read out in 19 fields when it is read out, and the display time of each field must be controlled. Therefore, when generating the field address counter of the read address, a 19-base counter counter19 (0 to 18) is designed first. Table 2 shows the relationship between counter19 and the field address counter: The display time of each field is realized by a comparator, and the grayscale and brightness can be flexibly corrected by changing the value in the comparator.

The LED display requires 32 zones to light up at the same time, using parallel data processing to reduce hardware consumption and system operating frequency. Increase the refresh rate. Since the memory can only read one data at a time, it is necessary to use partition latching and then output the 32 zone data in parallel.

The row address and column address have the same principle as the write address generator. Here we mainly introduce their priorities. The data is already separated in bit planes, so if you want to display 32 area data at the same time, the area address should have the highest priority, followed by the column address, then the row address, and finally the field address. The connection method with the memory is the same as the write address.

4 Simulation waveform

The simulation waveform of the bit plane separation module is shown in Figure 4: RGBdin[23..16] is the high eight bits of the input data, rgb_regroup_output[23..16] is the high eight bits of the output data, flag is the input data valid signal flag, and flag_delay85 is the output valid signal flag.

The waveform analysis is as follows:

The first 7 of the first 8 data of the input data are all 00h, and the 8th is 02h. After the 8 data are bit-separated, the output is shown in Table 3. It can be seen from Table 3 that the bit-separation realizes the reading from right to left after the first 8 data are transposed.

Figure 5 is the simulation waveform of the write address. It can be seen that the field address has the highest priority. When the field address is 7h, the column address is increased by 1, when the column address is 63h, the row address is increased by 1, and when the row address is 7h, the area address is increased by 1. Similarly, it can be seen that the carry order of the read address in Figure 6 is: when the area address is 1Fh, the column address is increased by 1, when the column address is 63h, the row address is increased by 1, and when the row address is 7h, the field address is counted according to the 19-field principle. When the row address is 7h in Figure 6, the field address is not increased by 1. Figure 7 is the duty cycle signal controlled by the field address counter. This signal is connected to the enable end of the row scanning signal of the display driver board, and the display time is controlled by controlling the scanning signal, thereby realizing the grayscale.

5 Conclusion

Aiming at the refresh speed and grayscale control problems encountered by the LED video display system, this paper proposes a field partition storage technology and introduces its principle and implementation in detail. Through waveform simulation and engineering application, this method solves the problems of image flicker and large brightness loss in the LED display control system, and its grayscale and brightness control can be flexibly corrected.