Current mode integrator circuit based on new CCCII

In analog electronic circuits, people have long been accustomed to using voltage as a signal variable and determining the function of the circuit by processing voltage signals. This has led to the birth and development of a large number of voltage signal processing circuits, or voltage mode circuits.
However, as the frequency of the processed signals becomes higher and higher, the inherent disadvantages of voltage-type operational amplifiers begin to hinder their application in high-frequency and high-speed environments. One of the disadvantages of voltage-type operational amplifiers is that the product of its -3 dB closed-loop bandwidth and closed-loop gain is a constant. When the bandwidth extends to the high-frequency region, the gain decreases proportionally; the second disadvantage is that its maximum conversion rate of output voltage under large signals is very low, generally only 0.2 to 20 V/μs.
In recent years, the huge potential advantages of current as a signal variable in signal processing have been discovered and tapped, leading to the development of a new type of circuit - current mode circuit. People have found that current mode circuits can solve a series of problems encountered by voltage mode circuits and obtain better performance in terms of speed, bandwidth, dynamic range, etc.

1 Second-generation current-controlled current conveyor CCCII
The second-generation current-controlled current conveyor element originated from CCII, but because there is a parasitic resistance between the input terminals X and Y of the internal circuit of CCII, and the transmission characteristics do not take this resistance into account, the voltage tracking between the X and Y terminals of CCII cannot reach the ideal level. CCCII uses the characteristic that the parasitic resistance of the X terminal is controlled by the internal DC bias to achieve the characteristic of adjustable voltage.
In 1996, scholars Alain Fabre and others proposed the second-generation current-controlled current conveyor circuit based on the translinear loop characteristics, and the subsequent CCCII circuits are basically implemented based on the translinear loop characteristics.
1.1 Linear transconductance principle
The main performance of the translinear circuit is obtained by means of the transconductance parameter of the bipolar transistor being proportional to its collector current. The proportional relationship between the transconductance parameter and its collector current is: in a closed loop containing an even number of forward biased emitter junctions, and the number of junctions arranged in the clockwise direction is equal to the number of junctions arranged in the counterclockwise direction, the product of the clockwise emitter current density is equal to the product of the counterclockwise emitter junction current density.
For bipolar transistors, the relationship between the collector current Ic and the base-emitter junction voltage VBE is its core relationship. This relationship can be expressed as:

In formula (1): VT is the thermal voltage, which is about 26 mV at room temperature; the reverse saturation current, which is sensitive to temperature, increases by about 9.5% for every 1 degree Celsius increase, and is approximately proportional to the emitter area. Differentiating formula (1) yields:

Formula (2) shows that the transconductance gm of an ideal BJT is a linear number of the collector static current IC, which is due to the logarithmic relationship between IC and VBE. In a closed loop containing n BJT base-emitter junctions, if some method is used to forward bias them and turn them on, the sum of the junction voltages should be equal to zero, that is:

Figure 1 shows a simplified TL loop, which contains 4 PN junctions. Each PN junction actually represents the base-emitter junction of each BJT in the loop. The current marked on each junction is the forward bias current of the junction, that is, the collector current IC of the BJT.

Substituting equation (2) into equation (3), replacing VBE, we get:

Where: Isj represents the reverse saturation current of each junction. Since the emitter area of ​​each junction may be different, it may also be composed of BJTs with different polarities. Since the TL loop is simplified, Isj may not be equal; Vtj represents the thermal voltage of each junction. For most application circuits, it can be assumed that the thermal voltages of all junctions are equal. Therefore, equation (4) can be expressed as:

A series of logarithmic sums of zero can be rewritten as a series of product terms of 1, so equation (5) can be written as:

In order to achieve the zero sum of the node voltage values ​​in the loop of equation (5) and the zero sum of the logarithms of the IC/IS current ratio, while maintaining a reasonable operating current, the TL loop must be paired, then it meets two basic conditions, namely: the number of nodes in the TL loop must be an even number; the number of nodes arranged in the clockwise direction and the number of nodes arranged in the counterclockwise direction must be equal. Assuming that the TL loop is symmetrical and satisfies the above two conditions, equation (6) can be expressed as follows:

The left and right sides of the formula are the products of the IC/IS terms of the forward-biased emitter junctions arranged clockwise and counterclockwise, respectively. Since the emitter junction reverse saturation current ISK in the TL loop is proportional to the area of ​​the emitter region, ISK can be expressed as follows: ISK=AKJSK, where AK is the emitter region area of ​​the Kth junction and JSK is the reverse saturation current density that is independent of the geometry. Assuming that JSK of each junction is equal, equation (7) can be rewritten as follows:
In a translinear loop, the emitter region area ratio is very important. Usually, in order to achieve certain desired performance and results, the emitter region area ratio is carefully designed and changed. When considering the emitter region area ratio in the TL loop, equation (8) can be expressed as follows:

In equation (9), λ is the area ratio coefficient.
When λ=1, the translinear principle can be expressed as:

Equation (10) shows that under the condition of λ=1, the product of the clockwise collector current in the TL loop is equal to the product of the counterclockwise collector current, which is the most concise expression of the translinear principle.
1.2 Circuit symbol and port characteristics of CCCII
The input and output port characteristics of CCCII can be expressed in matrix form:

The X terminal is the current input terminal, the Y terminal is the voltage input terminal, and the input current is zero; the same as CCII is that the X terminal voltage does not accurately follow the Y terminal input voltage, but is related to the X terminal parasitic resistance.

The positive and negative signs in the matrix represent CCCII+ and CCCII-, respectively. For CCCII+, IX=+IY, for CCCII-, IZ=-IX, and RX is the parasitic resistance of the X port, which is controlled by the bias current IB inside CCCII. The circuit symbol and zero pole representation of CCCII are shown in Figure 3.

2 Cascode CCCII Design
2.1 Cascode Current Mirror
In the current transmitter, the current mirror is an indispensable circuit model. Generally speaking, a current mirror is expected to have high current transmission accuracy, high output resistance, low input voltage and minimum output voltage.

The basic current mirror model shown in Figure 4 is difficult to achieve high current transmission accuracy and high output resistance due to the modulation effect of its own channel length. The common source and common gate current mirror shown in Figure 5 can obtain higher current transmission accuracy and output resistance than ordinary current mirrors. 2.2 Common source and common gate current mirror CMOS CCCII design circuit
Figure 6 is a CCCII circuit based on the basic current mirror, which includes a transconductance circuit composed of M1~M4, and basic current mirrors M5~M6, M7~M8, M10~M11, M12~M13. The basic current mirrors M5~M6, M9~M11 provide bias current IB to the transconductance circuit. Since the output impedance of the basic current mirror is low, the proportion of bias current IB transmitted to the transconductance linear circuit is small. The output terminal Z is connected to the output terminal of the basic current mirror, and the output impedance is low.

The CMOS CCCII current transmitter circuit shown in Figure 7 can be realized by using a common source and common gate current mirror. M1 to M4 form a translinear loop to realize a voltage follower, and M9 to M12, M17 to M12 form a common-phase transmission circuit to mirror the X-terminal current IX to IZ. M5 to M8, M13 to M16 form a current mirror with an amplification factor of 1 to provide a DC bias for the translinear loop. Changing the basic current mirror to a common source and common gate current mirror can not only increase the output impedance, but also increase the transmission accuracy.

2.3 Performance simulation of compositive source and common gate CMOS CCCII
Based on TMSC 0.18um CMOS process parameters, HSPICE software is used to simulate the performance of compositive source and common gate CMOS CCCII current transmitter, and the circuit is powered by 1.5 V. From the matrix relationship, we first observe the change of IZ with IX.
It can be seen that, as reflected in the theoretical derivation, in the absence of any current error, a higher transmission accuracy can be obtained. It can be observed that IZ changes with IX and follows IX well.
3 Design and simulation of current mode integrator circuit
3.1 Design of current mode integrator
Based on the compositive source and common gate CMOS CCCII, adding a resistor to the X end, adding a capacitor to the Y end, and changing it to the current input end can form a current mode integrator circuit. The schematic diagram is shown in Figure 9.

Assuming that the initial voltage of capacitor C is zero, according to the CCCII port characteristics, we get:

The above formula shows that the output current I0 is the integral of the input over time. 3.2 Current mode integrator simulation
Based on the TMSC 0.18μm CMOS process parameters, the HSPICE software simulation was used to simulate the current mode integrator with typical sine excitation and square wave excitation.
When a sine wave is input to the integrator, the input and output waveforms are shown in Figure 10.

When a square wave is input to the integrator, the input and output waveforms are shown in Figure 11.

Finally, the frequency response characteristics of the integrator are simulated, as shown in Figure 12.

Through public analysis, when the excitation source uses a sine signal and a square wave signal respectively, the output results of the integration circuit should be a cosine signal and a triangular wave signal. As shown in Figures 8 and 9, the operation results of this integration circuit are in good consistency with the theoretical results, which proves the correctness of the design of this integration circuit.

4 Conclusions
The current-controlled current conveyor is already one of the most commonly used modules in the current mode circuit. This paper proposes a COMCS CCCII current conveyor based on the common source and common gate, which improves the output impedance and current transmission accuracy, and designs a current mode integration circuit based on this CCCII circuit. Using TMSC0.18μmCMOS process parameters and using HSPICE software simulation, the simulation results verify the transmission accuracy, output impedance and feasibility of the common source and common gate current conveyor, and when the excitation source uses a sine and square wave signal, this integration circuit is verified, and the simulation results show that it has high accuracy. Therefore, this integration circuit can replace the traditional integration circuit in many applications and has broad application prospects.