Realization of high-speed data acquisition system for traveling wave fault location in power transmission lines

1 Introduction
Accurate fault location of high-voltage transmission lines in power systems is one of the effective ways to ensure safe and stable operation of the system. Modern traveling wave positioning is to achieve accurate fault location by comprehensively analyzing the sampling values ​​of the voltage and current traveling waves that appear on the line after the fault occurs, and determining the exact time when the fault traveling wave head arrives at the measuring point on the line. The transient traveling wave signal after a short-circuit fault occurs in the transmission line has different speeds and attenuation for different frequency components. The shape and polarity of the wave head are related to the change of the wave impedance at both ends of the line, and the amplitude is closely related to the time of the fault occurrence, which makes the traveling wave prone to distortion during propagation, reducing the ability to judge the accurate arrival time of the traveling wave and the recognition of the traveling wave reflection wave. For the acquisition of high-speed transient traveling wave signals with extremely fast change speed and extremely short change process, high-speed A/D conversion units, a large number of data storage units, high-speed addressing and fast storage are required.
In order to use a single-chip microcomputer to sample μs-level or even ns-level high-speed transient signals, a technology based on GPS synchronization and hardware circuits to achieve high-speed data acquisition, high-speed addressing and storage is studied, ensuring the real-time acquisition of high-speed transient signals. This improves the accuracy of fault location of power transmission lines.
Since the acquired signals are high-frequency signals, the conventional method is limited by the operating speed of the single-chip microcomputer itself. The use of computers not only increases costs, but also increases the difficulty in signal processing of high-frequency, long-distance multi-channel signals, and sometimes it is impossible to distinguish the authenticity of the acquired signals. By effectively expanding the periphery of the 8051 single-chip microcomputer, the acquisition and storage are realized by hardware during data acquisition, and the 8051 single-chip microcomputer performs data processing and communication after the acquisition is completed, which better solves the contradiction between the two. The
sampling frequency of the high-speed data acquisition board we developed is 20MSPS; the A/D conversion word length is 8 bits, and the sampling rate is variable; the storage capacity is 512K bytes, which meets the ISA bus standard and other characteristics. It can be widely used in power measurement , relay protection and fault location.
2 Hardware System
For high-speed data acquisition technology, the most important thing is the system resolution, accuracy and throughput rate, especially the system throughput rate, which is the most critical technical indicator that distinguishes high-speed data acquisition from general data acquisition. In the specific implementation of hardware, two aspects need to be considered: (1) the conversion time of the A/D converter. (2) the storage time of the converted data [3].
This paper uses the DS80C320 microcontroller as needed. Under the condition of a clock frequency of 33MHz, the single-cycle instruction execution time is 110ns, giving full play to the performance of the high-speed A/D conversion chip. The hardware circuit block diagram is shown in Figure 1. It consists of CPU1 and CPU2 basic systems, video flicker ADC converter, cache RAM, dual-port RAM, address counter, sampling frequency control, timing control and decoding circuit.

CPU1 is mainly used for data acquisition and communication with PC, CPU2 is used to receive GPS time message, GPS time message can be read by CPU1 from dual-port RAM2 connected to it at any time. High-speed dual-port RAM IDT7130 (2k×8 bits) and IDT7134 (4k×8 bits) are selected, and judgment circuit is internally provided to prevent conflict caused by simultaneous operation of a certain unit. The first dual-port RAM IDT7134 is mainly used by CPU1 to store collected data, synchronization time information and working status, etc., for PC to access regularly, and also to receive commands from PC. The second dual-port RAM IDT7130 has a capacity of 2K bytes and is mainly used for CPU1 and CPU2 to exchange GPS synchronization clock information.
2.1 High-speed A/D conversion
A/D conversion uses flash ADC device AD9048, with a maximum conversion rate of 35Ms/s and a resolution of 8 bits. The internal clock-locked comparator of AD9048 can make the encoding logic circuit and output buffer register work at a high speed of 35 MSPS, and avoid the need for sample-and-hold circuit (S/H) and track-and-hold circuit (T/H) in most systems. AD589, AD741, 2N3906, etc. form a voltage-adjustable circuit, which is provided to RB of 9048, and RT is grounded. AD9618 is used as an input buffer amplifier [4]. Since the data output of AD9048 does not have a three-state gate control, 74LS241 is used as a three-state gate control at the output. Whether AD9048 works depends on the input conversion pulse signal, and sampling is performed on the rising edge of the pulse signal. The conversion pulse comes from the output of the 8254 divider in the sampling frequency control circuit.
2.2 High-speed addressing
For high-speed data acquisition systems, A/D conversion should not be controlled by the CPU. After each ADC conversion, the control circuit sends a corresponding signal to write the ADC conversion result into a unit of the high-speed cache RAM, and then add 1 to the address counter until the address counter is full and a sampling end signal is generated. The control signal blocks the RAM write signal, and the highest bit of the binary address generator is used to notify the host through an interrupt that the sampling is completed.
The address formation circuit can be cascaded by several synchronous counters according to the number of address bits. Five 74LS163s can form a 19-bit address formation circuit. The counter generates an address every time it receives a pulse, and the initial value of the address can be cleared by the timing control circuit. If a circular address is used, after the count is full, the carry signal is used to force the synchronous preset level of the counter to change, so that the counter is restored to the initial value and enters a new round of counting.
2.3 Fast storage
The data transmission rate of the serial communication between the MCU and the host PC often cannot meet the real-time requirements. The maximum data transmission rate of the DMA channel does not exceed 5Mb/s [1]. This is obviously unable to meet the sampling speed of up to 20Mb/s in this system. In order to solve the contradiction between high-speed data acquisition and low-speed data transmission, in the MCU system, the data storage uses a dual-port RAMIDT7134, and a 4k-byte buffer is established between the host PC and the MCU. The MCU only needs to store the pre-processed sampled values ​​into the buffer through one port, and the host PC takes data from the buffer through another port. This
solves the contradiction between high-speed sampling and low-speed data transmission and can meet the requirements of real-time acquisition and control.