The structural principle of HV632
The block diagram of HV632 is shown in Figure 2. The working principle is briefly described based on the structure diagram: 8-bit binary bus data is input into the Data Latch through the D1~D8 ports, and is latched at the rising and falling edges of the shift clock. Each 16 Shift Clock pulses form a group, so 32 8-bit binary data can be latched. The data read in at the rising (or falling) edge of the first Shift Clock pulse is latched into Data Latch1 and corresponds to the high-voltage output HVout1. Similarly, the last 8-bit binary data is latched into Data Latch32 and corresponds to the high-voltage output HVout32. The data latched by each data latch will be compared with the output of the 8 B Counter in the Comparator. When the data in the latch matches the output of the 8-bit counter, the high-voltage output HVout jumps. Because the 8-bit counter is a reversible counter, there will be two matching situations in a complete reversible counting cycle. As the D~D8 inputs are different, the output pulse width will change accordingly, thereby achieving the effect of pulse width modulation.
Logic
The HV632 structure block diagram shown in Figure 2 contains two Logic parts, one of which refers to the logic part connecting the comparator and the XOR gate. The circuit of this part is actually a D flip-flop with a set function edge. The set signal acts through BLANK. When BLANK is high, the high-voltage output is all low. In addition, BLANK also plays a role in the counter. Therefore, when introducing the pin function of the chip, it is pointed out that the BLANK signal has the function of resetting the counter and high-voltage output. The other part of the Logic refers to the part connected with the input signal CSI and Shiftclk and the output signal CSO. The function of this circuit is to realize the input and output of the chip select signal. The arrival of each input signal CSI pulse will generate a chip select output pulse. Each CSI and CSO signal is separated by 16 Shift Clock pulses. Because Shift Clock is double-edge triggered, 32 8-bit binary data can be read between a group of CSI and CSO signals to achieve 32-channel output. The simulation waveform of this structure is shown in Figure 3.
High voltage output section
The high-voltage output part realizes low-voltage driving high-voltage. Its circuit is simulated, so it is described and simulated using Spice language. The final result shows that the circuit does realize low-voltage driving high-voltage. Its structure is described as follows using Spice language:
The simulation results are shown in Figure 4.
The input signals have such a logical relationship A=C=~B, which is determined by the output of the previous logic structure connected to this structure. The highest potential of the three input signals does not exceed 5 V. It can be seen from the figure that when A is high, the output Y=0; when A is low, the output Y=Vpp, Vpp is 80 V high voltage, thus achieving low voltage driving high voltage.
Other parts
Data Latch uses an edge-triggered D flip-flop composed of a two-choice selector to achieve data latching: when the falling edge of CP arrives, the output Q changes with the change of the input D; when the rising edge of CP arrives, it plays a latching role. The data latch has a simple structure and is easy to integrate.
8b Counter (8-bit counter) is a single-clock structure 8-bit reversible counter with a trigger composed of a two-choice selector as its main body and an addition and subtraction control module. It has an asynchronous set function. Its set signal is BLANK, which is valid at a high level.
2HV632 output waveform
Figure 5 shows the output waveform of the HV632 chip. In the figure, D8~D1 is the 8-bit counting result output by the 8b Counter. During simulation, the input DS-D1 of the 8-bit data bus selects 11111101. At t1, the output of the counter is 00000010, which is exactly the inversion of the 8-bit input signal. At this time, the two groups of signals match, and the output HVOUT22 jumps. Since the counter is a reversible counter, when D8-D1 decreases to 00000000, it increases by 00000000 again until it is added to 00000010, that is, it matches again at t2, and HVOUT22 jumps again. It can be seen from the figure that the pulse width from t1 to t2 is determined by the 8-bit bus input. As the input of DS-D1 changes, the output pulse width will change accordingly, thereby achieving the effect of pulse width modulation.
Conclusion
HV632 is suitable for flat panel displays, such as FED (field luminescent display), and supports pulse width modulation grayscale conversion with higher display resolution. HV632 is not only suitable for FED, but also for polymer liquid crystal, vacuum fluorescent tube and electroluminescence. It is also suitable for high data rate display applications, especially for products that need to reach more than 20 MHz and high speed and output voltage between 12 and 80 V. Using HV632 can also reduce the total number of components, save space, and reduce losses, heat generation and costs.
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