Analysis of compensation technology for linear voltage regulators

A Bode plot with three poles and one zero will be used to analyze the gain and phase margin. Assuming a DC gain of 80dB, the first pole occurs at 100Hz. At this frequency, the slope of the gain curve becomes -20dB/decade. The zero at 1kHz changes the slope to 0dB/decade, and the gain curve becomes -20dB/decade at 10kHz. The third and final pole at 100kHz finally changes the gain slope to -40dB/decade.

It can also be seen that the unity gain point (0dB) crossover frequency is 1MHz. The 0dB frequency is often called the loop bandwidth. The phase shift plot shows the effect of different distributions of zeros and poles on the feedback signal. The sum of the phase shifts is calculated based on the distribution of zeros and poles. The phase shift of the pole at any frequency (f) can be calculated as follows:
Pole Phase Shift = -arctan(f/fp)
The zero phase shift at any frequency (f) can be calculated as follows:
Zero Phase Shift = -arctan(f/fz)
Is this loop stable? To answer this question, we only need to know the phase shift at 0dB (which is 1MHz). No complicated calculations are needed.

The first two poles and the first zero distribution change the phase from -180° to +90°, which ultimately causes the network phase to shift to -90°. The last pole appears at 0dB in the decade. Using the zero phase shift formula, this pole produces a phase shift of -84° (at 1MHz). Adding the original -90° phase shift, the total phase shift is -174° (which means the phase margin is 6°). This loop may cause oscillation.

NPN Regulator CompensationThe
pass transistor of the NPN regulator is connected in a common collector manner. An important feature of all common collector circuits is low output impedance. This means that the pole within the power supply range appears in the high-frequency portion of the loop gain curve. Since the NPN regulator does not have an inherent low-frequency pole, it uses a technique called dominant pole compensation. In this case, a capacitor is integrated into the IC, which adds a pole at the low-frequency end of the loop gain.

[page] The dominant pole (P1) of the NPN regulator is generally set at 100Hz. The pole at 100Hz reduces the gain to -20dB/decade until the second pole (P2) at 3MHz. At P2, the slope of the gain curve increases by another -20dB/decade. The frequency of the P2 point depends mainly on the NPN power tube and the associated drive circuit, so this point is sometimes called the power pole. Because the P2 point appears at a loop gain of -10dB, it means that the phase shift at the 0dB frequency (1MHz) will be small.

To determine stability, it is only necessary to calculate the phase margin at the 0dB frequency:
the first pole (P1) produces a -90° phase shift, but the second pole (P2) only adds a -18° phase shift (at 1MHz). This means that the phase shift at 0dB is -108° and the phase margin is 72° (very stable). It should be noted that the loop is obviously stable. Since two poles are required to make the loop reach a -180° phase shift (unstable point), and P2 is located at a high frequency, its phase shift at 0dB is very small.

Compensation of LDO Regulators
The PNP pass transistor in the LDO regulator is connected in a common emitter mode. It has a higher output impedance than the common collector mode. Due to the influence of load impedance and output capacitance, a low-frequency pole appears at low frequencies. The frequency of this pole (called load pole, denoted by Pl) is obtained by the following formula:
F(Pl) = 1/(2π×Rload×Cout). From this equation, we can see that compensation cannot be achieved by simply adding a dominant pole.

To explain why this is the case, assume that a 5V/50mA LDO regulator has the following conditions:
At maximum load current, the frequency of the load pole (Pl) is:
Pl = 1/(2π×Rload×Cout) = 1/(2π×100×10-5) = 160Hz
Assume that the internal compensation adds a pole at 1kHz. Due to the presence of the PNP power tube and the drive circuit, a power pole (Ppwr) will appear at 500kHz.
Assume that the DC gain is 80dB. Rl = 100Ω (value at maximum load current), Cout = 10uF.

It can be seen that the loop is unstable: the poles PL and P1 each produce a -90° phase shift. At 0dB (40kHz in this case), the phase shift reaches -180°. In order to reduce the negative phase shift (prevent oscillation), a zero must be added to the loop. A zero can produce a +90° phase shift, which will offset part of the effect of the two low-frequency poles. Basically all LDO regulators need to add this zero in the loop. This zero is generally obtained through a characteristic of the output capacitor: the equivalent series resistance (ESR).

Using ESR compensation LDO
equivalent series resistance (ESR) is a common characteristic of every capacitor. The capacitor can be represented as a series connection between a resistor and a capacitor. The ESR of the output capacitor creates a zero in the loop gain, which can be used to reduce negative phase shift. The frequency value at which the zero occurs is directly related to the ESR and the output capacitor value: Fzero = 1/(2π×Cout×ESR). Using the example in the previous section, we assume that the output capacitor value Cout = 10uF and the ESR of the output capacitor = 1Ω. Then the zero occurs at 16kHz.

How to add this zero to make an unstable system stable:

The bandwidth of the loop is increased so the 0dB intersection frequency moves from 30kHz to 100kHz. The zero adds a total of +81° phase shift to 100kHz. That is, the negative phase shift caused by PL and P1 is reduced. Because the pole Ppwr is at 500kHz, it only adds -11° phase shift at 100kHz. Accumulating all zeros and poles, the total phase shift at 0dB is now -110°. That is, there is a +70° phase margin, and the system is very stable. This also explains that the output capacitor with the correct ESR value can generate a zero point to stabilize the LDO system.