MOSFET Selection Strategy in Synchronous Boost Converter Design

In the field of personal computer applications, MOSFET losses increase further as the switching frequency of synchronous boost converters developed for core DC-DC converters moves towards the 1MHz-2MHz range. The problem is compounded by the fact that most CPUs require higher currents and lower voltages. If you consider other parameters that dominate the loss mechanism, such as power supply input voltage and gate voltage, we have to deal with more complex phenomena. However, this is not the whole story, we also encounter secondary effects that can greatly exacerbate the losses and reduce the power conversion efficiency (ξ).

These secondary effects include breakdown losses and losses due to parasitic resistances such as equivalent series resistance ( ESR ) of capacitors and inductors, board resistance and inductance, and MOSFET package parasitic inductance . Other secondary loss mechanisms are the charging and discharging of the MOSFET electrode capacitances, including gate-source capacitance (Cgs), Miller gate-drain capacitance (Cgd), and drain-source capacitance (Cgs).

As the frequency gets higher, the losses due to the body diode reverse recovery become more significant and must be considered. Now, it is clear that selecting the MOSFET for a synchronous boost converter is no longer a trivial exercise and requires a solid method to select the best combination combined with a good understanding of all the above issues. This article will discuss all these effects in detail and will show you how to make this selection.

Conduction losses:

Since the current flowing through the Rdson of the MOSFET will generate resistance losses in the device, the losses M1 and M2 of the MOSFET shown in Figure 1 can be calculated by the following two equations:

in:

PCHS = high-side (HS) MOSFET conduction losses;

PCLS = low-side (LS) MOSFET conduction loss;

Δ = Duty Cycle ≈ Vout/ Vin

Iload = load current

Rdson = MOSFET on resistance

Vin = Power input voltage

Vout = output voltage

Since Δ and Iload are determined by the application, Rdson must be chosen to be as small as possible.

Figure 1: Simplified synchronous boost converter showing the parasitic inductance of the MOSFET.

Dynamic loss:

Dynamic losses are losses caused by the switching of HS and LS MOSFETs. These losses can be calculated using the following two equations:

in:

PDHS = HS MOSFET dynamic losses;

PDLS = LS MOSFET dynamic loss;

tr = rise time;

tf = fall time;

fs = DC-DC converter switching frequency;

Vd = body diode turn-on voltage;

The other parameters are the same as above. Obviously, we need to minimize the rise and fall time of the MOSFET. These two parameters depend on the Miller capacitance , which is usually represented by the gate-drain charge (Qgd). The lower the Qgd, the faster the MOSFET switches.

The switching losses in the LS MOSFET are rather negligible compared to the conduction losses since Vin is 12V and Vd is approximately 1V.

In this case, we must select the HS MOSFET with the lowest possible Qgd. This cannot be done by isolating the Rdson, as each of them depends on the die area. Most MOSFET manufacturers design their MOSFET devices to meet the requirements of HS or LS MOSFET, but actually hit the trade-off between switching speed and MOSFET on-resistance, i.e. Qgd and low Rdson.

Figure 2: HS MOSFET power losses with the Z-axis as a function of current on the X-axis and switching frequency on the Y-axis.

Figure 2 shows the power losses of a HS MOSFET. Clearly, the combination of high current and high frequency quickly leads to high losses. The correct choice of MOSFET is fundamentally concerned with overall high power conversion efficiency (ζ) and high reliability.

Reverse recovery loss

Another loss mechanism is due to the loss caused by body diode recovery. This is due to the HS MOSFET making the "on" state into the body diode. The body diode takes an infinite time to turn off, during which time the HS MOSFET will experience losses. The reverse recovery loss can be calculated by the following equation:

in:

Qrr = reverse recovery charge.

Furthermore, this loss mechanism is dependent on the switching frequency fs, since it is a form of switching loss. While the reverse recovery is due to the LS MOSFET body diode, the losses occur in the HS MOSFET.

Here, the selection criteria for the LS MOSFET is to obtain the lowest possible Qrr and suitable Rdson.

Figure 3: Power loss due to reverse recovery.

Breakdown loss:

Shoot-through losses are encountered when the LS MOSFET is turned off by the gate driver while the HS MOSFET is being turned on. During the transition, the gate-drain capacitance couples the drain voltage to the gate through the potential divider formed by Cgd and Rg//Cgs. If this coupled voltage is greater than the threshold voltage Vgth, then the LS MOSFET will be turned on, creating a low-resistance current path through the HS and LS MOSFETs , ultimately causing excessive losses. The equation governing the gate voltage relative to ground is shown below:

in:

Vg (t) = gate voltage;

a = slew rate of drain voltage;

Rg = total gate resistance including gate driver;

Cgs = capacitance between gate and source;

Cgd = capacitance between gate and drain;

Obviously, the larger the Cgd, the larger the coupling voltage.

Figure 4: Breakdown.

Taking the limit of the above equation is:

That is, infinite slew rate gives the equation:

The above equation expresses the theoretical worst-case scenario with no cross-conduction. If the MOSFET meets this condition within the worst-case parameter range—that is, minimum Cgs, maximum Cgd, and minimum Vgth—then no cross-conduction will be observed in any application.

Figure 5 is an oscilloscope graph where the upper trace is the LS MOSFET drain voltage and the lower trace is the LS MOSFET gate voltage. If the observed LS MOSFET gate voltage (green trace) reaches a voltage greater than Vgth, then we can observe breakdown and zeta loss. Ideally, you want a peak of a few hundred millivolts. The lower trace is the typical fingerprint of breakdown, allowing us to identify the problem by measuring the voltage from gate to source.

Figure 5: Identifying breakdown.

Effect of gate inductance:

The circuit layout of the gate drive circuit is extremely important to set the appropriate MOSFET switching frequency. Figure 6 is a three-dimensional representation of the gate voltage on the Z axis, the gate inductance on the Y axis and the time on the X axis. The figure shows the dynamic effect of the gate pin capacitance on the waveform. Gate voltage ringing can cause unstable switching, resulting in a loss of efficiency ζ and increased electromagnetic radiation. The gate pin must be kept as short as possible to avoid this effect.

Figure 6: Gate drive ringing.

Optimized gate drive voltage:

The gate drive voltage amplitude controls the switching behavior of the MOSFET in the following manner:

* Higher gate drive voltage means higher capacitor charging and discharging losses, given by:

Pcloss=CXV2Xfs

* Higher drive voltage means lower Rdson, therefore lower power loss, thus improving ζ;

* The gate voltage amplitude also affects the rise and fall times of the MOSFET.

The optimum gate drive amplitude that satisfies all of the above conditions and produces the highest ζ can be determined experimentally using different voltage amplitudes to determine the best performance point. Based on the mathematical solution to the problem, Figure 7 shows a three-dimensional graph of the optimum gate drive voltage on the Z axis as a function of the leakage current on the X axis and the switching frequency on the Y axis. Obviously, the gate drive voltage should never exceed the level recommended by the data sheet for high reliability operation.

Figure 7: Optimizing gate drive voltage.

Optimized power input voltage:

The industry standard for power input voltage for DC-DC converters used in the computer market is 12V, but is this the optimal value? To help answer this question, let's examine the impact of input voltage on ζ:

* The higher mains input voltage obviously translates into lower current from the mains and higher ζ value of the AC-DC converter (silver box).

* Higher supply input voltage means higher dynamic losses in the HS MOSFET.

* Higher supply input voltage means higher conduction losses in the LS MOSFET due to increased duty cycle.

The optimum input voltage may be derived experimentally or mathematically. Figure 8 shows a three-dimensional representation of the optimum input voltage on the Z axis as a function of load current on the Y axis and switching frequency on the X axis. Power supply input voltage levels are determined by industry standards for the computer market. If you are designing a two-stage isolated DC-DC converter, it is worth considering this in the process of determining the optimum intermediate voltage for your particular application.

Figure 8: Optimized power supply input voltage.

Device packaging

When choosing a device for your application, another parameter you have to control is the package. The most popular packages available for power MOSFETs are SO8, DPAK, D2PAK, and others. The most important package parameters are:

Package thermal resistance: This obviously limits the power dissipation and controls the heat dissipation design in the package;

* Choose the smallest thermal resistance possible;

* Package parasitic inductance: The package parasitic inductance extracted by the MOSFET has a great impact on the switching speed and ultimately affects the dynamic loss. The smaller the parasitic inductance, the shorter the switching time;

*Package parasitic resistance: This parameter is usually hidden in the Rdson value;

The best package for a given application should have the lowest parasitics and thermal resistance while meeting specific requirements.

Optimized working conditions

Maple provides a very exciting and effective tool for studying and understanding the physical phenomena in power circuits such as MOSFET. Based on the above discussion, we can say that the basic choices of switching frequency, gate drive, power input voltage, and circuit layout greatly affect the losses of MOSFET switching devices and the overall conversion efficiency. These choices must be made to minimize these losses.

References:

[1] A. Elbanhawy, "Effect of Parasitic Inductance on switching performance" in Proc. PCIM Europe 2003, pp.251-255

[2] A. Elbanhawy, "Effect of Parasitic inductance on switching performance of Synchronous Buck Converter" in Proc. Intel Technology Symposium 2003

[3] A. Elbanhawy, "Mathematical Treatment for HS MOSFET Turn Off" in Proc. PEDS 2003

[4] A. Elbanhawy, "A quantum Leap in Semiconductor packaging" in Proc. PCIM China, pp. 60-64

About the author:

Alan Elbanhawy is the director of computer and telecommunications at Fairchild Semiconductor International’s Advanced Power Systems Center. He holds a bachelor’s degree in electrical engineering and has 38 years of engineering experience in power supply design and R&D management. He can be reached at Alan.Elbanhawy@fairchildsemi.com.