Masterless parallel inverter power supply control technology-EEWORLD

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1 Introduction

With the continuous development of the domestic power industry, more and more AC loads in power plants and substations require uninterruptible power supply in the event of a fault, and the requirements for the quality and reliability of AC power supply are also getting higher and higher. Therefore, how to improve the power supply quality and reliability of the inverter is the focus of inverter research.

There are many parallel strategies for inverter power supplies, including master-slave structure [1], using voltage-type inverter as the main module to control the system voltage, and current-type inverter to provide load current. There is an equivalence equation, and the structures and functions of each inverter in parallel are the same. There is signal transmission between each other, but there is no subordinate relationship. There is also a non-connected parallel method based on active and reactive power regulation [2].

With the development of control technology and the emergence of high-speed digital processing chips DSP, achieving high-quality AC output is no longer a problem; however, how to achieve redundant design of inverters is still the main problem that bothers developers. The popular inverter parallel technology on the market currently uses the system monitor to uniformly generate SPWM signals for synchronization and load balancing. The technical disadvantages of this inverter are: a single inverter cannot work and must be matched with a system monitor to work, so the performance-price ratio of a small system is not high; the reliability of the system depends on the reliability of the system monitor. Once the monitor is damaged, the entire system will be paralyzed; the AC output cannot be short-circuited, and short-circuiting will cause the danger of burning the inverter.

2 Masterless parallel inverter control method

There are many types of control methods that can be used for inverters, and each control method has its advantages and disadvantages. At the same time, using different control methods to form composite control can achieve the purpose of learning from each other's strengths and weaknesses and mutual assistance. Therefore, composite control is a development trend of inverter control methods. With the rapid development of control theory and digital processing chips, the realization of various advanced control methods has become possible. The digital control method of the inverter has become a research hotspot and development trend in the field of AC power supply in the future.

This solution adopts a composite control that combines various control methods, and a new principle design that combines self-synchronization and external synchronization. Its advantages are high reliability; it can be used alone or in a group, and is easy to configure; it uses an external electronic switch to facilitate the formation of other forms of inverter power supplies such as UPS and EPS; the system monitoring has three synchronous signals that can be staggered by 120 degrees, which is convenient for combination into a three-phase inverter power supply system; and the three phases are adjusted separately, and each phase can carry 100% unbalanced load.

System principle block diagram 1

3 Hardware design:

The hardware circuit of the parallel inverter module consists of a power processing main circuit, a control drive circuit, and a protection circuit. The system principle block diagram is shown in Figure 1. The DC/DC conversion circuit is a BOOST circuit, which uses a high-frequency loop for inversion, so there is no need to use an industrial frequency transformer, which reduces the volume. Its function is to use the DC-DC full-bridge high-frequency isolation boost to convert the DC 220V voltage into the voltage required by the PWM rectifier inverter circuit for use by the subsequent full-bridge inverter. The control system result is shown in Figure 2. After the output given current Ug is compared with the actual output voltage Uk, its error signal is compared with the sawtooth wave after the PI regulator to form a PWM signal. This signal is then used by the drive circuit to control the switching device IGBT in the BOOST circuit, so that the actual output voltage can track the given voltage. This system uses the PWM controller SG3525 to obtain the PWM control signal [3].

DC/DC conversion circuit control structure diagram 2

[page] The power processing of the inverter adopts a full-bridge circuit. After SPWM modulation, the output is filtered by the filter inductor and capacitor, and then directly connected in parallel with the output of other inverters. When it is required to switch quickly with the power grid, the system main monitor commands the switch action of the electronic switching box to realize the bypass switching with the power grid.

The control circuit DSP TMS320F2407A completes the functions of SPWM waveform generation, phase locking, control, current sharing, synchronous signal capture, data sampling, etc. The output voltage feedback signal is sampled using the analog/digital conversion module inside the DSP, and the voltage effective value outer loop control is completed through the digital PI controller to ensure that the output voltage effective value is steady-state and has no difference. The output of the PI controller is multiplied by the standard given signal, and after digital/analog conversion, it is used as the reference input signal of the analog part of the control circuit.

Neither the master-slave setting method nor the average current method can achieve redundancy technology, so the reliability of the parallel power module system cannot be well guaranteed; while the autonomous current balancing chip UC3902 is based on its unique performance, such as "high current balancing accuracy, good dynamic response, and redundancy technology can be achieved". The autonomous current balancing method is essentially that among the N parallel modules, the module with the largest output current will automatically become the master module, and the remaining modules will become slave modules. The voltage errors of each slave module are adjusted in turn to adjust the imbalance of load current distribution. Since there is no manual setting of which module is the master module among the N parallel modules, but they are randomly sorted according to the size of the output current, the module with the largest output current automatically becomes the master module. This control system can directly obtain the current balancing error signal by using this chip, which simplifies the complex current calculation of the control system and improves the system reliability.

The UC3902 integrated chip accurately adjusts the output voltage of the converter to match all output currents. In addition, this chip has a unique advantage in that it uses a differential mode load-balancing busbar, which greatly enhances the system's ability to suppress noise. The UC3902 current-sharing chip has the following characteristics when used in power supplies: (1) High current-sharing accuracy (2) Simple peripheral circuit design, not as complicated as UC3907 (3) Easy to hot-swap.

4 Software design part:

The main program of the control part mainly completes power-on detection, current-sharing calculation, synchronous capture, modulation calculation, SPWM wave output, and current limiting protection strategy.

4.1 Current-sharing calculation:

Theoretically, the parallel connection condition of DC/AC inverter modules is that the frequency, phase, amplitude, and internal resistance of the output voltage of each module are exactly the same, so that parallel operation can be achieved, and the current and power output of the parallel modules are completely balanced. In actual systems, due to the inevitable dispersion of the hardware of each module, the frequency and amplitude of the reference sinusoidal signal of each module will also have slight differences; the above differences will cause the phase and amplitude of the output voltage of each module to be unequal; the phase difference will cause active circulating current between modules, and the amplitude difference will cause reactive circulating current between modules.

According to the reactive power formula

，

It can be seen that (where N is the total number of parallel modules in the system, n represents the nth module, is the power factor, and is the current sharing difference), reducing can reduce reactive circulating current.

Reactive power current regulation can adopt a power deviation control strategy. The inverter detects the current sharing deviation value of this module through the module to adjust the voltage value output by this module, so that the reactive power output of each parallel inverter module is equal, so as to achieve the purpose of current sharing. In order to make the current of each parallel inverter reach the purpose of equalization, a current sharing loop is added to the control loop of each parallel inverter in addition to the voltage control loop. The control block diagram is shown in Figure 3 below. In the current sharing control, the current sharing difference signal is given by the current sharing chip uc3902, and the current sharing loop adopts incomplete differential PID control to reduce the impact on the entire system due to the data error of a single module. In order to ensure the feasibility and adjustment range of actual current sharing, the idea of fuzzy control is adopted to limit the voltage of the actual output of current sharing within a certain range (that is, the actual output voltage after adjustment is within the standard voltage), so as to ensure the reliability of current sharing. At the same time, the amplitude of single-step adjustment cannot be too large, generally within 1V, otherwise it will cause large circulating current fluctuations.

System closed loop control diagram 3

[page]4.2 Synchronous control strategy

In the inverter power supply system, in order to suppress the influence of the circulation between modules, the phase, amplitude and frequency of the output voltage of each inverter module must be consistent, which is the premise for realizing parallel control.

The parallel inverter of this system adopts a new principle design combining self-synchronization and external synchronization as shown in Figure 4. When there is an external synchronization signal, the inverter output can track the grid synchronization or the synchronization given by the monitor; when the synchronization control unit detects that there is no external synchronization signal for a period of time, the synchronization signal line automatically switches to the self-excitation circuit to ensure that the monitoring unit can work normally even if a fault occurs. This synchronous control method does not affect the parallel operation even if a module cannot output the synchronization signal due to a fault, thereby realizing a synchronization mechanism combining internal synchronization and external synchronization, which is a major feature of this system. The inverter uses the 2407A capture unit to capture the synchronization pulse and complete the synchronization with the mains phase and frequency in the interrupt program.

Synchronous control circuit 4

4.3 SPWM control strategy:

In the actual design process, a full comparison unit, a general timer 3, a dead zone generation unit and an output logic in the event manager (assuming EV2) are used to generate a single-phase four-way SPWM wave, which is output through four multiplexed I/O pins. The timer of TMS320LF2407A has four working modes. When the continuous increase/decrease counting mode is used, a symmetrical SPWM wave output will be generated. In this counting mode, the counter value starts to count upward from the initial value, and when it reaches the T3PR value, it starts to count downward until the counter value is zero (entering the interrupt service program) and then counts upward again, and so on. In the process of counter counting, the counter value is compared with the value of the comparison register CMPRx (x=4,5). When the counter value is equal to the value of the corresponding comparison register, the corresponding square wave output of this phase will flip level. In each carrier cycle, the output square wave will flip level twice. As long as the value of the comparison register CMPRx is rewritten according to the online calculation in each triangle wave carrier cycle, the duty cycle of the pulse can be changed in real time to obtain a complete cycle of SPWM pulses. The calculation of the duty cycle of each pulse relative to the carrier cycle is completed in the interrupt service subroutine of the timer.

4.4 Current limiting protection strategy The

current limiting protection adopts dual protection of hardware and DSP software. The DSP software protection adopts predictive control current limiting technology. During the current rising process, the continuous sampling current value after removing the abnormal current value of the sampling point and the slope of the continuous sampling current value are compared with the set value to predict whether the current is overcurrent. The overcurrent can be judged and processed in advance, so that the output control software generates a current waveform infinitely close to the standard waveform, greatly reducing the harmonic current, so as to better protect the normal operation of the load. The hardware protection adopts the overcurrent detection circuit of the driver module HCPL-316J, which mainly plays a protective role when the software current limiting fails or the overcurrent rises very quickly. The use of dual current limiting protection can greatly provide the safety and reliability of the system.

[page]5 Test results and analysis5.1

Voltage waveform after DC input and DC/DC DC boost

DC input and boosted voltage waveform 5

Figure 5 shows the voltage waveform after DC input and DC/DC boost. The voltage ripple is small and basically straight. When the voltage has a slight jitter, the voltage is kept stable through the adjustment of the DC voltage amplitude feedback, ensuring a good dynamic response.

5.2 Waveform diagram of module synchronization with mains

Synchronous waveform 6

Figure 6 shows the module and mains synchronization waveform. The phase difference between the two is close to 0, which ensures the parallel connection well.

5.3 Voltage waveform of parallel modules

Parallel waveform 7

Figure 7 is a parallel module diagram. It can be seen that the basic component is approximately sinusoidal, the distortion is very small, and the parallel effect is good.

6 Conclusion

The main control chip of this system is TI's dsp2407, which is fully digitally designed, with few control components, high stability, and high reliability SPWM drive signal output. It adopts UC3902 chip current sharing technology. Each inverter unit works independently and democratic current sharing simplifies a large number of software calculations, greatly improves the current sharing accuracy, and is easy to install in parallel. It adopts a new principle design combining self-synchronization and external synchronization. A single module and monitoring failure does not affect the normal operation of other modules, which greatly improves the system reliability. It can realize N+1 inverter unit parallel expansion, and the capacity of the power supply is greatly improved. It can be hot-swapped with power on, and it is easy to operate and maintain.

In short, the solution adopted by this system has the characteristics of high integration, high performance ratio, the simplest peripheral circuit, and the best performance indicators, which will bring huge economic and social benefits.

References:

1 Xing Yan, Research on Parallel Operation System of Inverters. [PhD Dissertation] Nanjing University of Aeronautics and Astronautics, 19991

2 Chen Hong, Parallel Technology of Inverter Power Supply. Nanjing: Journal of Southeast University, 2002.55～59

3 Li Yongfu, High Frequency Switch Active Inverter Technology. Beijing: DC Power Supply, 2004.39～44

Reference address：Masterless parallel inverter power supply control technology

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