Low-dropout (0V) regulator saves power in base stations

Telecom base stations and other equipment require multiple power supplies to meet different output voltage and output current requirements. The main power supply in the computer room is usually converted to +48V or -48V DC power first, then transmitted to various system devices as needed, and finally converted to a lower level power supply voltage.

A common design is to use a power module or an off-the-shelf converter (brick) to convert the 48VDC (or -48VDC) power supply to a lower power supply voltage, and then the power module or the circuit on the PCB board converts it to the required voltages. A typical example is the conversion from 48V input to 8.5V, which is usually electrically isolated from the 48V input.

The 8.5V power supply is converted into 7.5V (base station equipment) for RF power amplifiers and 5V, 3.3/3V for logic circuits, or 1.8V for FPGAs and processor cores. Considering the power supply current and power consumption indicators required by the system, a switch-mode buck conversion technology is used to generate a lower power supply from 8.5V, while the 7.5V power supply at the RF level is mostly implemented using a low-dropout linear regulator (LDO) to meet the low-noise requirements of the RF circuit.

The linear regulator will adjust the voltage difference between input and output according to the output voltage requirement, thus consuming a certain amount of power (the product of current and input/output voltage difference), which is manifested as the heat consumption of the adjustment tube. In order to improve the heat dissipation capability, designers have to compromise between the input/output voltage difference, power dissipation, and adjustment tube selection, so that it can reliably operate in the linear region (non-saturation, cutoff) within the specified load current and input voltage range. In the circuit introduced in this article, the input power supply voltage may change by 100mV with the system load, and the voltage difference may reach 900mV. It can be seen that the power supply voltage of 8.5V just meets the requirements. In this example, the nominal voltage difference of 1V is just acceptable.

Most so-called LDOs actually have a dropout voltage higher than 1V, so these devices require a larger voltage margin between the input and output. For a 1V dropout voltage, the power dissipated on the pass transistor is 1V×10A=10W. Such a large power dissipation requires the system to provide a reasonable thermal management solution, which will increase the cost of small heat sinks and related materials and assembly time. As shown in Figure 1, the temperature rise of a heat sink with a typical coefficient of 6.8ºC/W (such as the heat sink of Aavid Thermalloy) and a TO-220 package will be about 68ºC above room temperature (for simplicity, the RθJC derating coefficient and other thermal resistances are ignored). Considering the other power components inside the chassis, whose internal temperature is usually higher than the external ambient temperature, the heat sink may even operate at more than 100ºC. In order to ensure reliable operation of the system, it is obviously impossible to use a smaller heat sink in this case.

Figure 1: Typical 6.8ºC/W heat sink.

[page] The design requires a low RDS field effect transistor (FET) to reduce the voltage drop of the series regulator. Polarity considerations require the use of P-channel devices. However, the on-resistance of a P-channel FET with the same architecture may be more than twice that of an N-channel FET. In addition, the price of a P-channel FET is also relatively high.

For comparison purposes, we can examine the International Rectifier (IR) P-channel IRF9Z34N and N-channel IRFZ34, both of which have a breakdown voltage of 55V. At 100ºC, the P-channel device has an on-resistance of 100mΩ and can carry 12A, while the N-channel device has an on-resistance of only 40mΩ and can carry 18A. The P-channel device is about twice as expensive.

When providing 10A peak current, the on-state voltage drop of a P-channel FET is 1V, while the on-state voltage drop of an N-channel FET with a 40mΩ RDSon is 400mV. Another option is to use a PNP transistor, but even then the saturation voltage drop between the collector and emitter will reach 200mV. It is also possible to choose an ultra-low RDSon N-channel FET that exceeds the performance of bipolar technology, but such a device requires a higher gate drive voltage. If a method can be found to drive an ultra-low RDSon N-channel FET, the above problems will be solved.

This is also a design challenge faced by switch-mode converters. In order to drive ultra-low RDSon N-channel FETs, voltage bootstrapping technology can be used: a dynamic switching voltage is AC-coupled through a diode, and then the energy storage capacitor is charged to obtain an N-channel FET gate drive voltage higher than the output voltage. If a buck converter is included in the circuit board or power module, its switching signal can be used to generate the gate drive voltage required by the linear regulator.

That is, we can connect the switch node of the buck converter to a simple voltage doubler circuit. A common voltage doubler circuit is a half-wave series multiplier, also known as a Villard cascade circuit (Figure 2). Applying an AC voltage with an amplitude of ±Us to this circuit can quadruple the output, that is, 4Us is obtained at the output.

The circuit can generate an output of 4Us when the switch voltage swings Us relative to ground, while the buck converter switch node swings approximately from Vin to ground. Therefore, if the buck converter is supplied with 8.5V, the switch voltage entering the inductor is 0V to +8.5V, resulting in Us = 4.25V, as shown in Figure 2.

Figure 2: (a) Villard cascade voltage doubler circuit. (b) The voltage doubler circuit has a +V input and a +V switching amplitude, which produces a 2x (+V) output.

If the duty cycle of the converter is considered, further complex calculations are required, because the duty cycle is related to the input-output voltage ratio and the load. For the sake of discussion, we assume that the duty cycle is 50%, and a voltage of about 17V can be obtained using the circuit in Figure 2. When a higher output voltage is required, more voltage doubler circuits can be cascaded. A voltage doubler uses two diodes and two capacitors to generate a low current DC output (Figure 2a).

The 17V DC generated by the above circuit can be applied to a simple low-current linear regulator (such as the MAX1616) to provide gate drive for low RDSon N-channel FETs. The FET device is powered by 8.5V and outputs 7.5V to power the RF amplifier. The linear regulator output is adjusted through a potentiometer voltage divider feedback network. The circuit was tested using the MAX5060 evaluation board, the MAX1616 linear regulator, the N-channel power MOSFET, and other related components. The simplified schematic is shown in Figure 3, and the actual circuit is shown in Figure 4.

Figure 3: Block diagram of zero-dropout voltage regulator circuit.

How the Circuit Works

The MAX5060EVKIT step-down converter can generate 3.3V voltage, output current up to 20A, switching frequency is about 270kHz, and 3.3V output is generated from 12V input. Because the circuit in Figure 4 operates under light load conditions, the load current is only 1A, and the voltage waveform acting on the inductor has a duty cycle of 25%, and the swing is between ground level and 12V. Using this switching voltage to drive the voltage doubler circuit, a DC voltage of about 24V can be obtained at the input of the linear regulator (MAX1616). The actual voltage doubler output is 22.7V, which can provide sufficient drive for the linear regulator. The output of the linear regulator can drive the gate of a low RDSon N-channel FET (IRFZ24N).

An adjustable power supply is used to power the FET, allowing the voltage drop to be adjusted according to the range of input and output voltages. The gate of the FET is driven by the 22V output of the MAX1616 LDO, and the FET is always driven in the on state until the voltage of the voltage divider network R1 reaches 1.24V, then the FET driver is turned off to keep the regulator balanced.

[page] Resistor R2 and capacitor C2 control the dynamic characteristics of the loop by suppressing high-speed transient response and noise. Resistor R2 also acts as the linear regulator's own load to absorb the current when the FET is turned off. The output voltage value is set by selecting the resistor ratio of the voltage divider network. In this application, R1 is selected as a 250kΩ potentiometer, which allows the MAX1616 output swing to rise from 1.25V to more than 22V.

Observe the drop of the FET gate drive voltage under different input voltages and loads to measure the voltage difference, thereby determining the operating point where the circuit enters closed-loop control. Once the gate drive drops below the 22V that the MAX1616 LDO can provide, the circuit will enter the voltage regulation state. By measuring the difference between the input and output voltages at both ends of the adjustment tube, the voltage drop within the range of power supply voltage and load variation can be determined.

This method has been proven to be an effective way to determine the voltage drop of a linear regulator tube. It also reflects the RDSon of the MOSFET from the side. Figure 5 shows the performance test results of the circuit in the form of tables and graphs.

Conclusion

The circuit shown in Figure 4 provides a zero dropout regulator (ZDO) that can be implemented using an N-channel, low RDSon FET, with the gate of the MOSFET driven by a voltage doubler circuit. Reducing the output load reduces the voltage difference between the input and output, reaching zero when no load is applied. In high current applications, this circuit can reduce the pass transistor losses during the regulation process, thereby reducing the need for heat sinks and other thermal management techniques.

Figure 4: Zero dropout (ZDO) circuit schematic.

The LDO of the base station system requires a voltage difference margin of 1V. The use of ZDO can greatly reduce this margin. For applications that require an output current of 10A, the field effect transistor IRF1324 with an extremely low RDSon can be selected. Its RDSon is less than 1mΩ. The voltage difference of the ZDO built with this FET is ideally 1mV per ampere.

In the example provided in this article, the FET used can effectively reduce the power consumption of the pass tube even under the worst operating conditions. Considering the influence of load changes and other factors, only 100mV of voltage difference margin is needed, plus the 10mV voltage difference required for FET RDSon, the original 8.5V intermediate voltage can be reduced to 7.61V. The total voltage difference is 110mV, and the power consumption corresponding to 10A current is 1.1W, saving about 9W of power. Using surface mount devices can directly dissipate heat through the copper area of ​​PCB, so thermal management problems can be easily solved. In short, using IRF1324 can save the heat sink, reduce costs, simplify the installation process, and save 9W of energy consumption for the system.

Figure 5: Test results of the ZDO circuit shown in Figure 4.

ZDO还可用于电池供电系统，系统所能提供的压差裕量会随着电池的工作电压而发生显著变化，ZDO在这样的系统可有效延长电池的工作时间。

Table 1: Key performance of the zero-dropout regulator circuit.

Remark

This circuit is just a schematic and has only been tested under light DC load. Readers can further develop it to optimize dynamic load response and low input/output voltage drop characteristics.