Improving Bridgeless PFC Performance with Digital Control

As efficiency requirements continue to grow, many power supply manufacturers are turning their attention to bridgeless power factor correction (PFC) topologies. Generally speaking, bridgeless PFC can reduce conduction losses by reducing the number of semiconductor components in the line current path. Although the concept of bridgeless PFC has been proposed for many years, its implementation difficulty and control complexity have prevented it from becoming a mainstream topology.

As some low-cost, high-performance digital controllers designed specifically for power supplies are launched, more and more power supply companies are beginning to choose these new digital controllers for PFC design. Compared with traditional analog controllers, digital controllers have many advantages, such as programmable configuration, nonlinear control, lower number of components, and most importantly, the ability to implement complex functions (which are usually difficult to achieve with analog methods).

Most of today’s digital power controllers (e.g. TI’s Fusion Digital Power Controller UCD30xx) offer many integrated power control peripherals and a power management core, such as digital loop compensator, fast analog-to-digital converter (ADC), high-resolution digital pulse width modulator (DPWM) with built-in dead time, and low-power microcontroller, etc. They all benefit complex high-performance power designs such as bridgeless PFC.

Digitally controlled bridgeless PFC

Among other bridgeless PFC topologies, Figure 1 is an example of a bridgeless PFC that has been widely adopted in the industry. It has two DC/DC boost circuits, one consisting of L1, D1 and S1, and the other consisting of L2, D2 and S2. D3 and D4 are slow recovery diodes. The input AC voltage is measured by detecting the line and neutral voltages respectively with reference to the internal power ground. By comparing the detected line and neutral signals, the firmware can know whether it is a positive half cycle or a negative half cycle. In a positive half cycle, the first DC/DC boost circuit (L1-S1-D1) is effective, and the boost current returns to the AC neutral point through diode D4; in a negative half cycle, the second DC/DC boost circuit (L2-S2-D2) is effective, and the boost current diode returns to the AC line through D3. A digital controller such as UCD3020 is used to control this bridgeless PFC.

Figure 1: Digitally controlled bridgeless PFC
The bridgeless PFC is basically composed of two phase boost circuits, but only one phase is active at any time. Compared with the traditional single-phase PFC using the same power devices, the switching losses of the bridgeless PFC and the single-phase PFC should be the same. However, the bridgeless PFC current only passes through one slow diode (D4 in the positive half cycle and D3 in the negative half cycle) at any time, not two. Therefore, the efficiency improvement depends on the difference in conduction losses between one diode and two diodes. In addition, the efficiency of the bridgeless PFC can be further improved by fully turning on the non-current switch. For example: in a positive half cycle, S2 can be fully turned on while S1 is controlled by the PWM signal. When the flowing current is lower than a certain value, the voltage drop of MOSFET S2 may be lower than that of diode D4, so the return current partially or completely flows through L1-D1-RL-S2-L2 and then returns to the AC source. In this way, the conduction loss is reduced and the circuit efficiency can be improved (especially under light load conditions). Similarly, in a negative half cycle, S1 is fully turned on when S2 is switched. Figure 2 shows the control waveforms of S1 and S2.

Figure 2: PWM waveform of bridgeless PFC

[page]Adaptive bus voltage and switching frequency control

Traditionally, efficiency was specified at full load for both high and low line. Now, most applications such as computing servers and telecom power supplies require that efficiency should meet standard specifications in the 10%-50% load range in addition to full load. In most AC/DC applications, the system has a PFC and a downstream DC/DC stage, so we measure efficiency based on the entire system. If we want to improve the total system efficiency at light load, one way is to reduce the PFC output voltage and switching frequency. This requires knowledge of the load, which is usually done by measuring the output current using some additional circuitry. However, with digital controllers, this additional circuitry is no longer required. When the input AC voltage and DC output voltage are the same, the output current is proportional to the voltage loop output. Therefore, if we know the output of the voltage loop, we can adjust the frequency and output voltage accordingly. With digital controllers, the voltage loop is implemented in firmware. Its output is known, so it is very easy to implement this feature and the cost is much lower than using analog methods.

Current sensing via current transformer

One of the challenges of bridgeless PFC is how to sense the rectified AC current. As mentioned earlier, the AC return current (partially or entirely) may flow through the non-current switch instead of the slow diodes D3/D4. Therefore, the method of using shunts to sense the current in the ground path (usually used in traditional PFC) is no longer applicable. Instead, current transformers (CTs) are used for sensing, one for each phase (Figure 1). The outputs of these two current transformers are rectified and combined to produce the current feedback signal. Since only one current transformer has a rectified output signal at any time, even if they are combined, there is only one feedback current signal at any time.

Figure 3: Sense current waveform in continuous conduction mode

Figure 4: Sensed current waveform in discontinuous conduction mode
As shown in Figures 3 and 4, since the converter is placed directly above the switch, it only senses the switch current (just the rising part of the inductor current). In digital control implementation, the switch current signal is measured in the middle of the PWM on-time Ta. It is an instantaneous value, represented by Isense in Figures 3 and 4. Only when the current is a continuous current, the measured switch current Isense is equal to the average PFC inductor current (Figure 3). When the current becomes a discontinuous state as shown in Figure 4, Isense will no longer be equal to the average PFC inductor current. In order to calculate the average inductor current, the relationship between the midpoint sensed current Isense and the average inductor current should be established within a switching cycle, and this relationship should apply to both continuous conduction mode (CCM) and discontinuous conduction mode (DCM).

For a boost converter operating in steady state, the secondary voltage of the boost inductor should be balanced in each switching cycle:

Where Ta is the current rise time (PWM on time), Tb is the current fall time (PWM off time), VIN is the input voltage, VO is the output voltage, and it is assumed that all power devices are in ideal state.

From Figures 3 and 4, we can calculate the average inductor current Iave based on Isense:

Where T is the switching period.

Combining equations (1) and (2), we can obtain:

By using equation (3), the average inductor current Iave is expressed as the instantaneous switch current Isense. The desired currents Iave and Isense are the current references for the current control loop. After the actual instantaneous switch current is detected, it is compared with the reference, and the error is sent to a fast error ADC (EADC). Finally, the digitized error signal is sent to a digital compensator to close the current control loop.

[page] Dynamically Adjustable Loop Compensator

Total harmonic distortion (THD) and power factor (PF) are two very important criteria for determining PFC performance. A good loop compensator should have good THD and PF. However, since the input range of PFC is very wide, it can extend from 80Vac to up to 265Vac. Therefore, a compensator with high performance on low-voltage lines may not work well on high-voltage lines. The best way is to adjust the loop compensator accordingly according to the input voltage. This may be an impossible task for analog controllers, but it can be easily achieved for some digital controllers (such as UCD3020).

The digital compensator in this chip is a digital filter consisting of a second-order infinite impulse response (IIR) filter cascaded with a first-order IIR filter. The control parameters, the so-called coefficients, are stored in a set of registers. This register set is called a bank. There are two such banks, and they can store different coefficients. At any time, only one bank's coefficients are valid and used for compensation calculations, while the other is inactive. The firmware can always load new coefficients to the inactive bank. During PFC operation, the coefficient banks can be swapped at any time to allow the compensator to use different control parameters to adapt to different operating conditions.

Figure 5: VIN and IIN waveforms for low voltage line (VIN=110V, load=1100W, THD=2.23%, PF=0.998)

Figure 6: VIN and IIN waveforms of high voltage line (VIN=220V, load=1100W, THD=2.27%, PF=0.996)

[page] Improve PF at light load

Every PFC has an electromagnetic interference (EMI) filter at the input. The X-capacitors of the EMI filter cause the AC input current to lead the AC voltage, which affects the PF. At light load and high line voltage, the situation becomes even worse: the PF can hardly meet the strict specifications. To increase the PF at light load, we need to force the current to lag accordingly. How can we achieve this?

Figure 7: Measured VIN without delay
We know that the PFC current control loop constantly tries to force the current to match its reference. This reference is basically an AC voltage signal, just with a different magnitude. Therefore, if we can delay the voltage sense signal and use the delayed voltage signal for current reference generation, we can delay the current to match the AC voltage signal, thus improving the PF. This is difficult for an analog controller, but can be achieved with digital control in just a few lines of code.

Figure 8: Measured VIN is delayed by 300us

First, the input AC voltage is measured by the ADC. The firmware reads the measured voltage signal, adds some delay, and then uses the delayed signal to generate the current reference. Figures 7 and 8 show the test results of a 1100W bridgeless PFC. In this test, VIN=220V, VOUT=360V, and load=108W (about 10% of full load). Channel 1 is IIN, Channel 2 is VIN, and Channel 4 is the measured VIN signal with delay. In Figure 7, the measured VIN has no delay added, PF=0.86, THD=8.8%. In Figure 8, the measured VIN signal is delayed by 300us, in which case the PF is improved to 0.90. In addition, the PF can be further improved, but this will sacrifice THD because further delaying the current reference will produce more current distortion at the AC voltage crossover point. In Figure 9, the measured VIN is delayed by 500us, and the PF is improved to 0.92. However, the current is distorted at the voltage crossover point. As a result, THD got even worse, reaching 11.3%.

Figure 9: Measured VIN delayed by 500us
[page] Nonlinear Control

Compared with the current loop, the voltage loop control is less complex. In digital implementation, the output voltage VO is detected by an ADC and then compared with a voltage reference. We can use a simple proportional-integral (PI) controller to close the loop.

Where U is the control output, Kp and Ki are the proportional and integral gains respectively. E[n] is the DC output voltage error sampling value.

As mentioned earlier, one of the benefits of using digital control is that it enables nonlinear control. To improve transient response, nonlinear PI control can be used. Figure 10 is an example of nonlinear PI control. When the error is larger (usually in transients), the Kp gain used is larger. This will speed up the loop response when the error exceeds the set limit, and the recovery time is also shortened. For the integrator, it is another case. As we all know, the integrator is used to eliminate steady-state errors. However, it often causes saturation problems, and its 90° phase lag will also affect the stability of the system. For this reason, a nonlinear integral gain is used (Figure 10). When the error exceeds a certain level, the integral gain Ki is reduced to prevent saturation, overshoot and instability.

Figure 10: Nonlinear PI control.
Another advantage of digital voltage loop control is known as anti-integrator windup, which typically occurs when AC drops. When AC drops and the downstream load continues to draw current, the DC output voltage begins to drop while the PFC control loop still attempts to regulate its output. As a result, the integrator integrates and can saturate, a condition known as integrator windup. Once AC returns, the saturated integrator can cause the DC output voltage to overshoot. To prevent this, the firmware resets the integrator as soon as AC is detected and the DC output reaches its regulation point.

Digital controllers can also do more work, such as frequency jitter, system monitoring and communication, and can also provide flexible control, higher integration and higher performance for bridgeless PFC. In some high-end AC/DC designs, more and more designs are using digital controllers.