High Voltage and High Power PS ZVS PWM DC/DC FB Converter Digital Phase Shift Pulse Generator

1 Introduction

Since the output voltage of the power supply to be designed has a large range of variation (0-5KV), and the output current is kept adjustable between 3-6A; the more difficult part is the generation of phase-shift pulses of the PS ZVS PWM DC/DC FB converter. Currently, there are chips such as UC3875 and UC3879 on the market for realizing phase-shift PWM control; however, this type of chip is mostly used for converters with fixed output voltages, and the output voltage of the converter is low. Its control method is to feed back the output voltage to the chip, and the chip adjusts the phase shift angle of the phase-shift pulse according to the output voltage. If this type of chip is used to generate phase-shift pulses (such as UC3879), then the possible way is to control the phase shift angle of the phase-shift pulse by controlling the voltage at its feedback voltage input terminal; however, the defect of this type of chip is that its phase shift angle is difficult to control accurately; and in the case of ensuring that the output current is constant, the phase shift angle needs to be accurately controlled, so this paper designs a fully digital phase-shift pulse generation circuit.


2 Leading bridge arm phase-shift pulse generation circuit

The phase-shift pulse generation circuit in this paper mainly consists of four basic components, and each basic unit is responsible for generating a trigger signal. The basic unit circuit is shown in Figure 1. The basic unit consists of a digital comparator (74HC688), a latch (74HC373), a counter (4040), a GAL (GAL16V8), and a D flip-flop (74HC74). The counter (4040) and the GAL16V8 form a counter with a count overflow value of 400, and its input clock frequency is 8MHz; the reason why the GAL16V8 is used is that the count overflow value can be flexibly set during debugging, and the logical relationship is adjustable. The count value of the counter and the output value of the latch (74HC373) (the value is provided by 80C196KC through the bus) are used as the input of the digital comparator (74HC688). When the two are equal, a low-level signal is output, triggering the D flip-flop (74HC74) to flip the output. The CPU can control whether the counter works or not through DT50, and the D flip-flop can be initialized through DT10 and DT11. The logic relationship of GAL16V8 in Figure 1 is: Pins 2, 5, and 12 are ANDed and then ORed with pin 14, and outputted through pin 13; that is, when the counter counts to 400, it is reset or the CPU performs a forced reset. Pins 12, 2, and 5 are ANDed and then outputted through pin 15; that is, when the counter counts to 400, the comparator is prohibited from working and outputs 1. Pins 2, 5, and 12 are ANDed and then ANDed with pin 18, and outputted through pin 19 (GAL implements this relationship as follows: ); that is, when the comparator output is 0 or the counter overflows, a jump from 1 to 0 is generated to flip the D flip-flop. Pin 17 is the negation of pin 16 and is used by the CPU to set the value of the comparator action. In the figure, QD1 is the driving signal of the IGBT.

In fact, Figure 1 is the trigger pulse generating circuit of the upper arm of the leading bridge arm, and the trigger circuit of the lower arm is basically the same; except that it does not use latches (74HC373), but shares DB1~DB8 signals with the trigger circuit of the upper arm, that is, their pulse widths are equal; in order to achieve the alternating conduction of the upper and lower arms and prevent the delay required for direct conduction, when the upper arm trigger pulse jumps from 1 to 0, the trigger pulse generating circuit of the lower arm must have a certain delay, and the circuit of Figure 2 realizes this function. Its basic principle is that the CPU sets a number (i.e., delay time) to U11 (74HC373) through the bus. When this value is equal to the count value of 4040, the comparator 74HC688 outputs 0,

U7:B (D flip-flop) outputs 0, that is, CF2 outputs 0. CF2 is connected to the 14th pin of the lower arm trigger pulse generating basic unit GAL16V8 (the position corresponding to DT50 in Figure 3.1) to allow the lower arm trigger pulse generating circuit to start working. The QD1 signal in the figure is the trigger signal of the upper arm.

When it is 0, the counter (4040) starts working to determine the delay time. The CPU can preset the initial value of U7:B (D flip-flop) through DT31 and DT30, and can also control the comparator (74HC688) to work or not through DT40. In practical applications, U7:B (D flip-flop) is preset to 1, and it always outputs 0 after being triggered unless it is reset.


3 Generation circuit of phase-shift pulse

of lagging bridge arm The basic structure of the trigger pulse generation circuit of the lagging bridge arm is the same as that of the trigger pulse generation circuit of the leading bridge arm, as shown in Figures 1 and 2. However, in order to realize the pulse phase shift function of the lagging bridge arm relative to the leading bridge arm, a delay circuit is required. The circuit in Figure 3 completes this function. The CPU sets a number to U24 (74HC373) through the bus to determine the size of the phase shift angle. The signals YX1~YX8 of the comparator U26 (74HC688) are taken from the counter of the trigger pulse generating circuit of the leading bridge arm (Q1~Q8 of 4040 in Figure 1). When the input of the counter (U26) is equal, the phase shift angle output is 0, and the D flip-flop U17:A flips to output 0, that is, ZHK is 0, and ZHK is used to trigger the trigger pulse generating circuit of the lagging bridge arm to start working (the connection position of ZHK is equivalent to DT50 in Figure 1). Since the D end of U17:A is grounded, once ZHK outputs 0, it will always output 0 unless it is forced to 1 through T50. In addition, the comparator can be controlled by DX7.


4 Conclusion

The above gives a PS ZVS PWM DC/DC FB converter phase shift pulse generating circuit. The circuit can flexibly adjust the phase shift angle and change the trigger pulse width through the control of the CPU. It can be implemented with complex programmable logic devices such as CPLD according to the design idea of ​​this circuit.


References:

[1] Ruan Xinbo, Yan Yangguang; Soft switching technology of DC switching power supply; Science Press; 2000.

[2] Wang Cong; Soft switching power converter and its application; Science Press; 2000.

[3] Zhong Liping, Liu Chengfang; New phase-shift PWM controller UC3879 and its application in zero-voltage full-bridge converter; Foreign Electronic Devices; August 1996.