High Precision MOSFET Design Tips

As the personal computer industry moves toward 1V core voltages operating at 200A, the semiconductor industry is under tremendous pressure to meet those demands and provide the methods needed to tailor new devices for this market. In the past, MOSFET design engineers have simply gradually improved their performance to meet market needs and generally achieved satisfactory results.

Today, they face requirements that radically depart from passive or proactive design approaches that would have allowed them to deliver higher currents, higher efficiencies, and smaller footprints to meet the growing demands of the ever-shrinking volume resources allocated to DC-DC converters. To this end, this article proposes a surgical precision approach to designing MOSFETs for the needs of this market. This radical change is justified because the market is large enough to justify the expense and provide solutions that meet the market needs very well.

Figure 1: Boost converter.

MOSFET Design Methodology

The synchronous boost converter is the topology of choice for DC-DC converters in the personal computer industry and is widely used in other markets such as telecommunications. We will only consider this topology in this article, but the same approach may also be applicable to other topologies. We will try to derive an equation for calculating the optimal MOSFET die area based on two factors.

1. Its role in the circuit is a power switch MOSFET or synchronous rectifier;

2. The total losses associated with this particular MOSFET.

The choice of total losses as a determining factor is a direct result of the industry's need for higher efficiency and lower losses. A MOSFET optimized for die area provides the lowest losses when used in its intended application, i.e., a switching MOSFET or synchronous rectifier. Obviously, such an equation depends on the specific process used to manufacture the device and the specific device design that utilizes that process.

By relating device area to physical application parameters, we can examine the different effects these parameters have on the device and, in the best case, we can precisely design a device to the application requirements, or in other words, a MOSFET for a specific application. This approach enables the power semiconductor industry to produce power devices that meet requirements every time and eliminate guesswork from the design process, resulting in shorter and less expensive development cycles.

To simplify the derived equations, we restrict the loss calculation to two dominant loss sources:

1. Conduction loss;

2. Dynamic or switching losses.

Until now, people have ignored the charging and discharging of the capacitance between the gate and source and between the drain and source. Given the switching frequency of 300KHz and the input voltage of 12V, these two loss sources account for a very small percentage of the total device loss. On the other hand, the introduction of these two loss sources does make the mathematical derivation process using Maple software more complicated, making the derived equations too complex to use it to study the impact of application parameters on device area.

Top MOSFET losses

Let's consider these two sources of losses in a switching MOSFET: the first is conduction losses or ohmic losses, and the second is dynamic losses. Conduction losses are simply I2R x duty cycle losses, while dynamic or switching losses are caused by the limited voltage between the drain and source and the current flowing through the MOSFET as it turns on or off. The losses can be calculated as follows:

(1)

in:

tr and tf = rise and fall time;

Vin = input voltage;

ILoad = load current;

Fs = switching frequency;

RDSON = MOSFET on-resistance;

ΔPWM = duty cycle;

Rpackage = package impedance;

To calculate tr and tf, we need to make the following assumptions:

tr ≈ tf

For the switch, only the charge component Qgd from gate to drain is considered, since the gate charge Qg does not play any role in the switch.

in:

Qgd = gate or drain charge;

Kd = constant;

Id = gate drive current at gate threshold;

A = die area;

Substituting (1), we obtain:

(2)

Taking the first derivative of (2) — the die area A — we obtain:

(3)

Taking the second derivative, we get:

(4)

Equation (4) is positive, indicating that solving (3) for A will produce a minimum of the function. Solving for A, we obtain the minimum of the function Pdissipation:

(5)

The optimal die area may be calculated as follows:

(6)

Replacing ΔPWM with Vout/Vin and ID with VDrive/Rg, we get:

(7)

Because VoutILoad = output power = Pout

(8)

Note: Aoptimum is directly proportional to √Pout and inversely proportional to Vin