A New Current Limit Comparator

1. Introduction

Switching power supplies have been widely used in the fields of electronics, electrical equipment, and home appliances due to their small size, light weight, high efficiency, and stable performance, and have entered a period of rapid development. The basic working principle of a switching power supply is: Under different load conditions, the feedback control circuit stabilizes the output voltage by changing the duty cycle of the power switch tube. The feedback control circuit is divided into current mode and voltage mode. The current mode is widely used due to its advantages such as fast dynamic response, simple compensation circuit, large gain bandwidth, small output inductance, and easy current sharing.

The limiting current comparator is a very important part of the current mode control circuit. It generates different limiting currents for different load conditions to limit the peak current or average current on the inductor, thereby minimizing the output voltage ripple and improving power efficiency. For example:

The output current of the power supply corresponding to the heavy load condition is relatively large. At this time, a larger limit current should be set to ensure the output voltage is stable; the limit current corresponding to the light load condition is small. At this time, a smaller limit current should be set to stabilize the output voltage. Therefore, different load conditions correspond to different limit currents, thereby obtaining different duty cycles to ensure high power efficiency and small output voltage ripple.

In the traditional switching power supply control circuit, the current limit comparator structure is shown in Figure 1 (a). The detection current flows from M1 (sense MOSFET) into the network R1 composed of multiple switch tubes and resistors. The network changes the resistance value of R1 by controlling the switch tube to turn on or off, and obtains different duty cycles. Another reference current flows through a fixed resistance resistor R to generate a fixed reference voltage. When the voltage drop of R1 rises to the reference voltage along with the detection current, the comparator turns off the power tube to ensure the output voltage is stable. Its working principle is shown in Figure 2 (a). For example, the voltage on R1 rises from a to d, thereby turning off the power tube to generate a duty cycle. When the resistance value of R1 is changed, the voltage on R1 rises from a to f to obtain another duty cycle. It can be seen from Figure 1 (a) that the traditional switching power supply current limit comparator converts the two currents into voltages before comparing them. It requires a resistor network and switch tube that occupy a very large chip area. In addition, in order to ensure the resistance accuracy, laser trimming technology is generally required, which greatly increases the chip cost. Therefore, this paper proposes a new current limit comparator structure based on this.

Figure 1. Conventional and novel current limit comparator structures

Figure 2. Working principle of conventional and novel current limit comparator structures

2. New structure and principle

Figure 1 (b) shows the basic framework of the current limit comparator proposed in this paper, where Iref is the limit current generated by the current mirror, and its value is variable. The detection current flows from M1 (sense MOSFET) into the current comparator and is directly compared with the set limit current. When its value rises to the limit current, the power tube is turned off. By changing the limit current, different duty cycles are obtained. Its working principle is shown in Figure 2 (b).

Figure 3 is the specific circuit of the new current limit comparator proposed in this paper. Among them, M0- -M11 constitutes a current mirror network, which is used to set several limit current values ​​required by the power supply. Mc1- -Mc10 constitutes a current comparator, which directly compares the limit current with the detection current to produce different duty cycles (i.e. different on-times). The NAND gate and the inverter constitute a control circuit, which directly drives the power MOS tube to control its on or off. This current limit comparator uses a current mirror structure to replace the traditional resistor network to generate several limit currents required by the power supply, and uses a cascode structure to form a current comparator instead of a traditional voltage comparator to directly compare the two currents.

Figure 3 A new type of current limit comparator

M0 introduces the reference current through the current mirror. M2, M3, M4, and M5 generate four reference currents of different sizes in a certain ratio through M1. Then, they are transmitted to M7, M9, M11, and M5 through the current mirror. The four currents generate various limit currents required by the power supply in different combinations. The state machine that detects the output voltage of the power supply generates corresponding high and low level signals to set the required limit current by detecting the output voltage [4]. This circuit cleverly uses the output voltage of the state machine as the power supply voltage of the current mirror, which is connected to s0, s1, and s2 respectively, directly controlling the current mirror to turn on or off, generating the required limit current, thereby eliminating the need for a switch tube that occupies a very large chip area.

Since the current mirror network is used instead of the resistor network, the matching of MOS tubes in the process is much higher than that of resistors, thus avoiding the laser trimming technology used by the resistor network to ensure accuracy, greatly reducing the cost. In addition, the chip area occupied by the current mirror is much smaller than the area occupied by the resistor network, further reducing the cost. In addition, this paper cleverly uses the control signal output by the state machine directly as the power supply of the current mirror, so that the current limit comparator does not need a switch tube that occupies a very large layout area. For example, when s0 and s2 are connected to a high level and s1 is connected to a low level, there is no current in M9, and the sum of the currents in M7, M8 and M5, Mc1 and Mc2, is used as the limit current. In the traditional current limit comparator, in order to ensure that the on-resistance of the switch tube is very small, its width-to-length ratio is very large, thus occupying a large layout area. This structure cleverly omits the switch tube, further reducing the chip area and reducing costs. In order to meet the low power design, this paper sets the current in M5 as the minimum value of several limit currents, and there is always current. When the power tube is turned off, the control signals s0, s1, and s2 are low level, and only M5 in the current mirror network has current. Since its static current is very small, the circuit is low power. In the current limit comparator with a resistor network (actually a voltage comparator), it is generally necessary to generate a reference voltage of about 1V or more, so that the static current is relatively large when the switch tube is turned off. The current in M5 can be used as the limit current during normal operation, and can also prevent malfunctions caused by delays or noise in the state machine and current mirror.

Mc3- -Mc6 form a cascode structure as a current comparator.

The detection current is introduced into Mc8, which can be completed by using the structure in. Then it is mirrored to Mc5. When the main power tube starts to conduct, the current mirror detection current in Mc5 and Mc6 rises slowly. As long as the detection current is less than the limit current set at this time, at least one of Mc3 and Mc4 will work in the linear region, and Mc3 and Mc4 as a whole will present resistance characteristics. Because if Mc3 and Mc4 have been working in the saturation region, their current will definitely mirror the current in Mc1 and Mc2, that is, the limit current. This will lead to the contradiction that the current in Mc3 and Mc4 is not equal to the current in Mc5 and Mc6. Therefore, only when the current in Mc3 and Mc4 is equal to the current in Mc5 and Mc6, Mc3 and Mc4 will work in the saturation region.

When the detection current is equal to the limit current, the cascode outputs the average value of the power supply voltage and the ground to the inverter, which just reaches the inverter's transfer voltage. The inverter begins to flip the level, thereby turning off the power tube. Since the comparator adopts the cascode structure, its output resistance is very large. As long as the detection current just rises to the limit current, the inverter level can be flipped immediately to turn off the power tube, which has very high accuracy. The cascode structure replaces the voltage comparator to make the detection current and the limit current directly compared, and also avoids the inaccuracy caused by the offset voltage of the voltage comparator. For example, assuming that the offset voltage is 20mV and the minimum value of the resistor network is 5kΩ, the offset voltage will cause a detection current error of 4μA, which greatly affects the performance of the system. In short, the current limit comparator structure proposed in this article has great improvements in both the current mirror part and the current comparator part compared with the corresponding traditional structure.

3. Simulation

This paper uses the TSMC 0.25μm process model to perform performance simulation on the parameters set in Figure 3. Assume that the minimum limiting current, i.e. the current passing through m5, is 4μA, the limiting current controlled by s0 is 12μA, the limiting current controlled by s1 is 20μA, and the limiting current controlled by s2 is 36μA.

Figures 4-7 show the working conditions of the current comparator when the limiting current is 4μA, 16μA, 24μA and 40μA respectively. The duty cycles corresponding to the four currents are 10%, 40%, 60% and 100% respectively. The horizontal axis in Figures 4-7 represents the detection current, which slowly increases from 0, and the vertical axis represents the voltage at certain key points in Figure 3 changing with the detection current.

Figure 4 Characteristics of the current limit comparator when the limit current is 4uA

Figure 5 Characteristics of the current limit comparator when the limit current is 16uA

Figure 6 Characteristics of the current limit comparator when the limit current is 24uA

Figure 7 Characteristics of the current limit comparator when the limit current is 40uA

The working condition of the current limit comparator is now explained by taking Figure 4 as an example. At this time, the limit current is 4μA, the dotted line represents the output voltage waveform of the cascode structure, the black solid line represents the output voltage waveform of the inverter, that is, the input voltage waveform of the NAND gate, and the other two dot-dashed lines represent the gate voltage waveforms of Mc3 and Mc4 in the cascode structure.

From the dotted line, i.e., the output voltage waveform of the cascode structure, it can be seen that the working process of the current limit comparator is divided into five stages. The first stage: the detection current slowly rises from 0 to A. In this process, since the detection current is much smaller than the limit current, both Mc3 and Mc4 are forced to work in the linear region. The second stage: the detection current rises from A to B, and the output voltage of the cascode structure also rises, making Mc4 work in the saturation region and Mc3 work in the linear region. However, Mc4 has just entered the saturation region and is still affected by the channel modulation factor. It can be clearly seen from the figure that when the output voltage of the cascode structure rises with the detection current, the current in Mc4 slowly approaches the set limit current. The third stage: the detection current rises from B to C. At this time, the detection current has risen to the set limit current. Both Mc3 and Mc4 work in the saturation region. At the same time, the output voltage of the cascode structure also rises to the midpoint voltage of the subsequent inverter, and the power tube is turned off through the subsequent control circuit. The fourth stage: the detection current rises from C to D. At this time, the detection current is greater than the set limit current, forcing Mc5 to work in the linear region. Although Mc6 still works in the saturation region, it is affected by the channel modulation factor. In addition, Mc3 and Mc4 work in the saturation region. The fifth stage: the detection current continues to rise from D, forcing Mc5 and Mc6 to work in the linear region, and Mc3 and Mc4 to work in the saturation region. It can be seen from Figure 4 that when the detection current reaches 4.1μA, the power tube is turned off, meeting the system requirements. The working conditions of Figures 5 to 7 are similar to Figure 4. Figure 5 sets the limit current to 16μA. It can be seen that when the detection current reaches 15.97μA, the power tube is turned off. Figure 6 sets the limit current to 24μA. It can be seen that when the detection current reaches 23.82μA, the power tube is turned off. Figure 7 sets the limit current to 40μA. It can be seen that when the detection current reaches 39.6μA, the power tube is turned off.

The simulation results show that the new structure proposed in this paper can make the detection current reach the set limit current value very accurately and meet the system requirements. However, the figure shows that there is still a certain deviation between the detection current and the limit current (the maximum is 0.4μA). Through simulation analysis, it is found that this is caused by the error of the current mirror image caused by the channel modulation factor. If the gate width of the current mirror is increased, the accuracy can be further improved, but this will increase the area of ​​the chip to a certain extent. The design should be considered in compromise according to the system indicator requirements.

Finish

This paper proposes a new type of current limit comparator structure, which uses a current mirror structure to replace the traditional resistor network to generate several limit currents required by the switching power supply, and uses a cascode structure to form a current comparator to replace the traditional voltage comparator to directly compare two currents. This structure does not require a switch tube and a resistor network, which greatly reduces the chip area and reduces the cost. At the same time, it has the advantages of fast speed, low power consumption and high accuracy.