CPLD self-powered system using battery

A common industrial and consumer application is a system that samples environmental conditions such as GPS (Global Positioning System) position, voltage, temperature, or light at long intervals (e.g., once a minute). Increasingly, these systems are wireless and battery powered, waking up once a minute, taking a sample, transmitting the data to a central data collection terminal, and then going back to sleep. This design idea uses a small portion of an Altera EPM240-T100 CPLD (complex programmable logic device) in conjunction with some discrete capacitors, resistors, diodes, and MOSFETs to automatically wake a CPLD system from a completely powered-off state via an RC timer circuit. This approach minimizes power consumption in both situations: during sampling when power is on, and between sampling when the system is powered off (except for the RC circuit).

Figure 1 is a basic CPLD on/off timer. Q1 is an IRLML6302 P-channel MOSFET used as the system's power control switch. When the gate node is at VCC, R2 pulls up, and the power supply to the CPLD and the entire system is cut off, with only the RC circuit consuming a small amount of power. The CPLD has a control block, a 4.4MHz internal oscillator, a 3-bit register, and 6 I/Os. Figure 2 is the state machine for the control section. The output of the state machine is high, and all other outputs are low. The dotted line from power-off to power-on represents the time delay, which is

The RC circuit formed by R1 and C1 is measured when the system is powered off. The circuit is initialized when switch S1 is turned on. When S1 is closed, D2 pulls the gate node low, and Q1 turns on when the gate voltage is less than 0.7V of VCC. Less than 200ms after Q1 is powered on, the EPM240-T100 operates in the power-on state. The power-on state pulls the power node low, maintaining the gate voltage at 0.7V, keeping Q1 on after the switch is opened. The power-on state also pulls the charge node to VCC. This action charges the negative terminal of C1 to VCC. Since reset = 0, the control block enters the reset state and Register 1 is reset. Once S1 is opened, the control block enters the enable state and the enable signal is driven to 1.

Next, the sample and transfer circuit starts to operate, making the done signal 0. When the sample and transfer are completed, the done signal becomes 1 and the control block enters the save state. The save state charges capacitor C2 to CN according to the value in Register 1. The save state is active for 100ms, allowing the output to fully charge the 10mF capacitor. After 100ms, the control block enters the power-off state and stops driving the charge node and the power node. R4 pulls the power node high, while R2 pulls the gate node high.

When the gate node brings VCC-VTQ1 to approximately 2.3V, Q1 shuts off power to the system. All I/Os of the EPM240-T100 are in a high-impedance state and do not affect the gate node or the charge node. The charge node starts at VCC and begins to discharge through R1 when the power is turned off. Once the charge node drops to 2.3V, D1 pulls the gate node low. When the charge node reaches 1.6V, the gate node is at 2.3V and Q1 turns on. The time Q1 is on is slightly less than t of R1 and C1. The off time is equal to R1×C1 = 100,000×0.0001=10 s.

The device powers up in the Power-Up state but quickly transitions to the Sample state. The Sample state records the values ​​on capacitors C2, C3, and C4. These capacitors act as nonvolatile memory to store the number of previous power-up cycles. If the Register 1 value sampled on C4 to C2 is less than 7, the control block begins incrementing and the Register 1 value increases by 1. The control block then enters the Save state again and C2 to C4 are charged to a new binary value of 001. The device is powered down again. On the 8th power-up cycle, or about 80 seconds after power-up, the control block transitions to the Enable state, thus beginning a new sample and transmit sequence. This process repeats every 80 seconds. You can change this 80-second cycle by adjusting C1 and R1 to change the size of Register 1 and the count between enable cycles. Since the 80-second cycle consists of eight small power-up sample, test, and power-down cycles, the duty cycle of the power supply is less than 3%, so this scheme increases battery life by 33 times.