Discussion on Power Factor Correction of Electronic Ballast

This paper analyzes the power factor correction problem of electronic ballasts, focusing on the working principles of the three modes of active power factor correction (peak current control, fixed on-time, and fixed frequency average current continuous conduction mode), their advantages and disadvantages, and applicable occasions.

Keywords: Passive power factor correction, Active power factor correction, Peak current control, Fixed on-time, Frequency clamping, Leading (trailing) edge modulation, Discontinuous conduction, Critical conduction, Continuous conduction mode, Transition mode

The input circuit shown in Figure 1a is usually used in electronic ballasts . Since the capacity of the electrolytic capacitor CO is large and it stores a lot of charge during operation, there is input current only when the input voltage exceeds the voltage on the capacitor. Therefore, the current waveform is seriously distorted, and only a current spike pulse will appear near the voltage peak (as shown in Figure 1b). As a result, the power factor of the circuit becomes very low, about 0.5, and the input current harmonic content is very rich. According to the national standard GB/T17263-2002 and the European regulation EN63000-3-2, strict requirements are put forward for the content of each harmonic of energy-saving lamps and electronic ballasts above 25W. Many existing circuits cannot meet this requirement at all.

In order to reduce the harmonic distortion of the ballast input current, some special measures must be taken, usually called power factor correction (PFC) technology to improve its power factor. Generally speaking, there are two solutions for power factor correction: passive power factor correction (Passive PFC) and active power factor correction (Active PFC). The former has been introduced in a lot of information and is not the focus of this article. We mainly analyze the three modes of active power factor correction, their working principles, advantages and disadvantages, and applicable occasions.

The principle of passive power factor correction and common circuits

The principle of passive power factor correction is to increase the on-time of the input current, make the waveform of the power supply current close to the sine waveform of the voltage, and reduce its distortion. The initial solution was the current-following circuit.

It uses the circuit of Figure 2(a) to replace the capacitor CO in Figure 1. The power supply charges the capacitors C1 and C2 to the peak value of the input voltage through VD3. The voltage of each capacitor is at most half of the peak value of the input voltage. In this way, the capacitor can be charged within a range of 120˚, the input current time is extended, and the current is zero (dead zone) for only 33.3%. The power factor can be improved to about 0.9, but the voltage on the capacitor fluctuates greatly and the harmonic content is very high. It still cannot meet the requirements of the national standard GB/T17263-2002 and the European EN61000-3-2 standard for the limit value of each harmonic content (2nd to 39th harmonics). In addition, the peak coefficient of the lamp current is very large, and the lamp power fluctuates greatly, which is not good for human vision and lamp life.

The improvement of the current-following circuit is to use a double-pump circuit, and replace the circuit of Figure 2 (a) with the circuit of Figure 2 (b). It adds C3 and C4 on the basis of the former, feeds back the high-frequency signal, reduces the fluctuation of the DC voltage on the capacitor , and further reduces the current dead time and the lamp current crest factor. All indicators have been improved, but still cannot meet the requirements of the national standard GB/T17263-2002 for the limit value of each harmonic content. If some improvements and remedial measures are taken on the basis of the circuit of Figure 2 (b), the requirements of the standard can be met. Figure 3 is such an improved double-pump circuit. At present, many products in energy-saving lamps and electronic ballasts use it, and have passed the 3C certification.

There are other ways to improve the dual pump circuit. As long as the parameters of the feedback components and filter inductance are carefully adjusted (the EMI filter circuit at the input end has a great influence on THD and PF), the requirements for harmonic limits in the standard can be met.

A high-frequency pump circuit is also used in some electronic ballast circuits. Its specific form is shown in Figure 4. For this circuit, as long as the feedback capacitor values ​​of C4 and C8 are properly adjusted and the parameters of the filter inductors LO, L1, and L2 are reasonably selected, the requirements for harmonic limits can be met and the 3C certification can be passed. Its performance is better than the circuit in Figure 3 when the parameters are adjusted. However, the circuit has large losses and high requirements for feedback capacitors C4 and C8, filter circuits, and electrolytic capacitors, which are its shortcomings. There are some other forms of passive power factor correction circuits, but they are not the focus of this article and are limited by space, so they are omitted.

2. Basic principles of active power factor correction

The basic principle of active power factor correction can be explained by the simple circuit shown in Figure 5. It adds a key power factor controller IC that plays an important role on the basis of Figure 1. It controls the opening and closing of the MOS tube VT1, so that the input current becomes a series of triangular waves, and its amplitude changes according to the sine law of the input voltage, which can greatly improve the power factor of the circuit. This circuit consists of power MOS switch tube VT1, boost inductor L, boost diode VD, output capacitor C0 and APFC controller IC. The specific working conditions of the circuit are as follows

(1) When the switch tube VT1 is turned on

When VT1 is turned on under the control of the APFC controller outputting a high level (square wave) signal, Figure 5 becomes the equivalent circuit form shown in Figure 6. The switch tube VT1 is turned on, which is equivalent to the switch S1 being turned on. At this time, the diode is cut off due to the reverse bias of the output DC voltage VO, which is equivalent to S2 being disconnected. After rectification, a unidirectional sinusoidal voltage is obtained on the capacitor C1 (the capacity of the capacitor C1 cannot be too large), which will generate a current in the inductor L. Considering that the switching frequency of the switch tube is very high, generally exceeding 25kHZ, the input voltage uI can be approximately regarded as unchanged in the short time of half a switching cycle, and the rate of increase of the inductor current di/dt is a constant (Ldi/dt=uI). The inductor current rises linearly, and the magnetic energy LiL2/2 stored in the inductor also increases with the increase of the current.

When the peak value of the inductor current increases to a certain value ILP corresponding to the input voltage at that moment, the APFC controller outputs a low-level switching signal to turn off the switch tube VT1 and the current iL stops rising. Considering that the current rises linearly, there is

LΔi/Δt=uI,

Δi=ILP, Δt=ton represent the rise amplitude and rise time of the triangle wave respectively (see Figure 7).

Then ILP=uIton/L

It can be seen that when ton is a fixed value, the amplitude ILP of the triangle wave reflects the change of the input voltage uI at that moment.

(2) When the switch tube VT1 is turned off

The circuit of Figure 5 can be simplified to the form of Figure 7.

Since the inductor current iL cannot change suddenly, it can only decrease linearly from the original value ILP. The magnetic energy of the inductor is released and superimposed with the input voltage to charge the electrolytic capacitor CO. The voltage on the capacitor is obviously higher than the input voltage. Therefore, this circuit is called a boost APFC circuit. When the switch tube is turned off, the inductor current decreases and decreases linearly according to the linear law (Ldi/dt=VO-uI, which is also a constant under the condition that uI is approximately unchanged). Once the controller detects that the inductor current drops to zero, it outputs a control signal to turn on the switch tube again and start the next switching cycle.

Under the above control, the input current or inductor current is a series of continuous straight-up and straight-down triangle waves. As long as the peak value ILP of the triangle wave can follow and reflect the change of the input voltage, its average value, that is, half of its peak value, can change according to the sine law, making the power factor close to 1. Figure 8 is a schematic waveform of the current change of the inductor current or input current under the control of the APFC controller.

It can be seen that under the control of the APFC controller, the inductor current rises from zero to a certain value (proportional to the instantaneous value of the input voltage at that moment), then drops to zero, and rises again, and so on. There is no dead time when the current is zero, so it is called critical conduction mode (CrCM). It is a critical form or transition form between continuous conduction and discontinuous conduction. Therefore, some literature also calls it transition mode (TM) or boundary conduction mode (BCM).

To make the power factor close to 1, the controller needs to control two time points: the time when the current reaches zero and the time when the current reaches the peak. For the control of the former, the same control principle and means are adopted in various IC controllers, using the circuit shown in Figure 9. In the figure , the secondary winding of the boost inductor is connected to the zero current detection terminal (ZCD) of the IC through a resistor . Once the inductor current drops to zero, the induced electromotive force of the inductor changes polarity to about -1.8V. Using this feature, the zero current detection comparator outputs a high-level signal to the S terminal of the RS trigger, causing the RS trigger to flip, and the drive output OUT of the PFC controller becomes high. The positive switch signal will turn on the external MOS tube. The current flowing through the inductor rises linearly from zero again.

There are two solutions for controlling the time point when the peak current is reached, resulting in two different types of APFC controller ICs, which are discussed below.

Working Principle of Peak Current Control APFC Controller

How the peak current control APFC circuit controls its peak current can be explained by the simplified schematic diagram shown in Figure 10. The dashed box in the figure represents the relevant parts of the IC, and the rest are peripheral circuits connected to the IC. The unidirectional sinusoidal voltage output by the rectifier bridge is divided by resistors R1 and R2 and sent to pin 3. It reflects the change of the input voltage, and its value is about 2~4V. The DC voltage VO output by the boost diode is also divided by resistors R3 and R4 and added to the inverting input terminal INV (pin 1) of the voltage error amplifier (represented by EA in the figure) inside the IC. The signal reflecting the inductor current is drawn by the source resistor R8 of the external MOS tube.

Sent to the current detection terminal CS (pin 4). Pin 4 is connected to the inverting terminal of the current detection comparator (or peak current comparator) through the internal RC filter circuit, and the output VMO of the multiplier is connected to the non-inverting terminal of the comparator as the reference voltage of the comparator. The multiplier must have good linear transfer characteristics within a wide dynamic range, which is proportional to the product of its two input voltages, that is,

VM0=KVM1（VM2-VREF）

Considering that one of the inputs of the multiplier is obtained by dividing the output voltage VO, under normal circumstances, VO basically changes very little (when the output voltage is 400V, the peak-to-peak value of the voltage change is only about 5~10V) and is close to a stable DC voltage. In this way, the size of the multiplier output VMO is basically proportional to VM1, reflecting the input voltage that changes according to the sinusoidal law. Therefore, when the voltage drop generated by the current flowing through the inductor on RS reaches and exceeds the reference threshold VMO set by the multiplier output, the current detection comparator will output a control signal to the R end of the RS trigger, causing the RS trigger to flip. In this way, the IC's drive output OUT becomes a low level, turning off the external MOS tube, and the inductor current reaches its peak value and no longer increases. Obviously, under such conditions, the peak current is proportional to the input voltage at that moment.

Since the multiplier output also includes a component proportional to the APFC output voltage VO, if VO changes, for example, its value decreases, then since this input is added to the inverting input of the error amplifier, VM2- will rise, the multiplier output VMO will increase, and the current detection comparator will extend the on-time of the power switch tube , increase the energy stored in the boost inductor, and increase VO; conversely, it will shorten the on-time of the MOS tube and reduce VO, thereby achieving the purpose of adjusting VO to make its value tend to be stable. This pulse width modulation working mode is very common in switching power supplies .

From the above analysis, we can know that this control method uses the input voltage as the reference signal. Once the inductor current rises to the threshold value specified by the reference signal, the IC controller sends a shutdown signal to turn off the MOS tube, and controls the peak value of the triangular wave inductor current to be proportional to the input voltage. Therefore, this method is called peak current control method.

Theoretical analysis shows (see reference 1) that in this control mode, the on time of each triangular wave is constant, while the off time is variable. When the input voltage is low (near zero crossing), the off time is the shortest, so the switching frequency is the highest. This brings three problems: first, the high frequency leads to large losses in components, especially inductors, in the circuit; second, near zero crossing of the voltage, the input current distortion is large (see Figure 11), and the THD value becomes larger; third, a series of high-frequency triangular waves have very rich harmonic content, causing difficult electromagnetic interference. Therefore, after the ballast adopts this type of control chip, the EMC problem is more troublesome (see reference 2). In order for the ballast to pass the 3C certification, the filter circuit must be carefully adjusted.