Design of interleaved parallel symmetrical half-bridge full-wave rectifier circuit

As shown in the figure, let the symmetrical half-bridge full-wave rectifier circuit work in QSW mode, and the inductor current changes from positive to negative in all load ranges. Then, before the primary switch tube is turned on, the inductor current can be reflected to the primary side and flow through the body diode of the switch tube to be turned on, realizing ZVS. Moreover, when the load increases suddenly, the equivalent duty cycle of the output filter inductor can reach 100%, and there will be positive voltage added to the output filter inductor throughout the cycle to increase the current; when the load decreases suddenly, the equivalent duty cycle of the filter inductor can be 0%, and there will be negative voltage added to the inductor throughout the cycle to reduce the current. It has a dynamic response characteristic similar to that of a single-channel QSW circuit. By applying the staggered parallel technology, two symmetrical half-bridge full-wave rectifier circuits are connected in parallel (as shown in Figure 10), and the steady-state duty cycle is taken as 0.5, a complete output current ripple cancellation effect can be achieved, which greatly reduces the output filter. It has a symmetrical and fast dynamic response when the load increases and decreases suddenly.

Figure 9 Symmetrical half-bridge full-wave rectifier circuit and QSW operating waveform

Figure 10 Interleaved parallel symmetrical half-bridge full-wave rectifier circuit

Figure 11 is a symmetrical half-bridge current doubler rectifier topology. The current phases of the two output filter inductors differ by 180°. There is a similar inductor current ripple cancellation effect as in the dual-channel staggered parallel topology. When D=0.5, complete current ripple cancellation can be achieved (output current ripple is zero). When applied to loads that do not require high dynamic response, the steady-state duty cycle can be selected as 0.5, thereby greatly reducing the size of the output filter. However, for loads such as data processors that have high requirements for dynamic response, the full duty cycle of 0.5 cannot be used as the steady-state duty cycle. However, when D deviates from 0.5, its ripple cancellation effect will be greatly weakened, limiting the output filter parameters from being small and reducing the energy transmission speed of the power level. In this case, the interleaved parallel technology is used to interleave two symmetrical half-bridge current doubler rectifier topologies in parallel, as shown in Figure 12. This can achieve a ripple cancellation effect similar to that of a four-channel interleaved parallel QSW circuit (Dmax<0.5). At this time, if the steady-state duty cycle is set at 0.25, complete ripple cancellation can be achieved in the steady state, and the output filter inductance can also be made very small, thereby having a symmetrical fast dynamic response when the load suddenly increases (D: 0.25→0.5) and decreases (D: 0.25→0).

Figure 11 Symmetrical half-bridge current doubler rectifier topology

Figure 12 Interleaved parallel symmetrical half-bridge current doubler rectification topology and its principle waveform

It is worth pointing out that the topology of these staggered parallel structures is particularly suitable for the application of magnetic integration technology. Multi-channel inductor integration solutions and inductor and transformer integration solutions can be adopted [7][8]. This greatly reduces the total volume occupied by magnetic components, simplifies circuit layout and packaging design, and has significant advantages over discrete magnetic components.