Interleaved PFC control technology and its application to improve power conversion efficiency

Over the years, several innovative power factor correction (PFC) technologies have been introduced. One of the first innovative technologies was active power factor correction using a boost topology. Active power factor correction technology increased power density by eliminating the need for bulky passive PFC solutions. Another innovative technology was transfer mode PFC, which eliminated the reverse recovery current in the boost diode of the PFC pre-regulator, reducing the switching losses of the converter and improving system efficiency. The next innovative PFC technology used to increase power density and improve system efficiency is the interleaved PFC pre-regulator.

Power supply designers have been designing interleaved PFC converters for years, but due to the lack of suitable controllers, they have to be very careful in designing power supply control. To make interleaved PFC design easier, Texas Instruments (TI) has developed two interleaved PFC controllers: one for average current mode pre-regulators (UCC28070) and the other for interleaved transfer mode PFC pre-regulators (UCC28060). This article will discuss how to use interleaved PFC and its control techniques to increase power density, improve system efficiency and reduce system cost.

The interleaved PFC boost pre-regulator (Figure 1) consists of only two PFC boost converters that operate 180° out of phase, reducing the input current (IIN) caused by the inductor currents (IL1 and IL2). Since the high-frequency ripple currents of the inductors are in opposite phase, they cancel each other, reducing the input ripple current caused by the boost inductor current. The cancellation of the inductor ripple current allows the power supply designer to parallel the boost PFC pre-regulator while reducing the input ripple caused by the boost inductor, which can reduce the total inductor boost amplitude and/or reduce the size of the EMI filter. In addition, the interleaved PFC pre-regulator has less than 50% of the high-frequency output capacitor root mean square (RMS) current (ICOUT) compared to the single-stage topology. The reduction in the high-frequency boost capacitor RMS current can reduce the number of boost capacitors by up to 25%. Do not confuse the number of boost capacitors with the number of capacitors required in the design, which is generally determined by the hold-up time.

Interleaving a PFC pre-regulator can reduce the total inductor energy required for a design by up to 50% compared to a single-stage pre-regulator. To illustrate this, consider the formula for the inductor energy required for a single-stage PFC (ES(L)) and the total inductor energy required for an interleaved PFC (EI(L1+L2)). For the same power level, if the same inductor value is used in both designs, the total inductor energy required for the interleaved design is only half that of the single-stage design. In fact, the reduced inductor energy of the interleaved design can reduce the magnetic volume by up to 32%.

By comparing the conduction losses (PCS) of a single-stage PFC with the overall conduction losses (PCI) of an interleaved PFC, it can be seen that an interleaved PFC pre-regulator can reduce conduction losses by up to 50% compared to a single-stage power factor correction converter. The reduction in conduction losses will allow the interleaved PFC pre-regulator to have higher efficiency at higher voltages (when conduction losses are the dominant loss).

In the past, power supply design engineers were forced to use discrete circuit control schemes to control interleaved PFC pre-regulators. To help power supply design engineers implement interleaved designs, TI has launched two interleaved PFC controllers, of which the UCC28060 controller not only allows two transfer mode PFC pre-regulators to operate in an interleaved manner, but also uses a constant on-time control technique that does not require current detection. This technology eliminates the need for a current sense resistor at the source of the boost FET, and current detection is only required in the peak current limiting circuit that protects the boost FET. The peak current limiting comparator is designed to be triggered at 200mV, which is less than 1/6 of the voltage of the current sensing signal normally required for a transfer mode PFC controller. Due to the current sensing function, this innovative technology greatly reduces conduction losses. Figure 1 shows the schematic diagram of an interleaved PFC pre-regulator using the UCC28060 control IC.

Figure 1: Schematic diagram of an interleaved PFC pre-regulator using the UCC28060 control IC.

Although interleaved PFC pre-regulators can improve efficiency by reducing conduction losses, they actually reduce the light load efficiency of the converter when switching losses (PS) dominate. The following equations account for the switching losses of the two-phase interleaved boost diode and boost FET, where VDS and IDS are the drain-source switching voltage and drain current of the FET, respectively, variables tr and tf are the drain-source rise and fall times of the FET, Coss is the drain-source parasitic capacitance of the FET, Qg is the gate charge of the FET, Vg is the gate drive voltage applied to the FET gate drive to turn it on, variable fs represents the switching frequency of the converter, and variable IRR represents the reverse recovery current of the boost diode. From this equation, it can be seen that the total losses caused by COSS, Qg, and IRR are twice that of a single-stage PFC pre-regulator. Turning off one of the interleaved phases and entering single-phase operation under light load conditions can improve efficiency under light load conditions.

To improve light-load efficiency, the UCC28060 has an optional built-in phase management circuit. Enabling this function can increase the system's light-load efficiency by 1 to 3% (Figure 2).

Figure 2: UCC28060 efficiency improvement through phase management.

The second control IC used to control the interleaved PFC is the UCC28070. This control IC allows the two average current mode PFC boost stages to interleave. To ensure the highest efficiency of the pre-regulator, the IC can sense the current with a current sense transformer. In addition, to ensure proper regulation and current sharing, the UCC28070 can work with a single voltage loop and two separate current loops.

PFC boost pre-regulators using current sense transformers usually require the detection of the current of the boost diode (D1) and the boost switch (Q1). Generally speaking, the current sensing circuit consists of two current sense transformers (CT1 and CT2), two rectifier diodes (D), two reset resistors (RR), and a current sense resistor (RS) (Figure 4). In the interleaved PFC pre-regulator structure, the current of each phase may need to be sensed. To reduce system cost, TI has developed a current synthesis technology that can directly synthesize the boost diode current without sensing the boost diode current, thereby saving a current sense transformer (CT2), a rectifier diode, and a reset resistor in the circuit.

Figure 3: Current synthesis technology reduces the number of current sense transformers.

In summary, interleaved PFC pre-regulators can improve power density by reducing the number of capacitors and the total number of inductors. Interleaved power converters can reduce conduction losses and improve overall system efficiency. In the past, power supply design engineers had to be cautious about interleaved PFC control because there was no PFC controller. To help in the design process and make interleaved PFC control easier, TI has introduced innovative interleaved PFC controllers. The UCC28060 is designed specifically for transfer mode interleaved PFC and has built-in phase management to improve light load efficiency. The UCC28070 is designed specifically for interleaved average current mode PFC and uses innovative current synthesis technology, which reduces system cost by reducing the number of components required for current transformer current sensing.