Discussion on SSN Solution Based on Ansoft Simulation Analysis

Power integrity PI (Power Integrity) refers to the fluctuation of power output due to the increasing number of switching devices and the decreasing supply voltage, which affects the working state of the chip and the quality of the output signal. Therefore, in addition to analyzing reflection, crosstalk and EMI in signal integrity, how to obtain a stable and reliable power system has become a new key research direction.
PI (Power Integrity) and SI (Signal Integrity) are inseparable. In the past, EDA simulation tools generally simply assumed that the power supply was absolutely stable when performing signal integrity analysis, but this is inconsistent with the actual situation. The new generation of signal integrity simulation must be based on reliable power integrity. Since power integrity not only emphasizes the stability of power supply, but also includes the fact that it is always inseparable from power supply in actual systems. Therefore, how to reduce the noise of the ground plane is also a part that needs to be discussed in power integrity. This article mainly discusses how to reduce SSN in solving signal integrity problems.
1 Increase decoupling capacitors to suppress SSN
This article takes the design of a circuit board downloaded from the Ansoft website for digital signal processing research as an example to illustrate the process of increasing decoupling capacitors to suppress SSN.
The size of the power layer and ground layer of the circuit board is 22.86 cm×15.24 cm. Both the power layer and the ground layer are copper layers with a thickness of 0.037 mm. The middle routing layer is the 3rd to 6th layer. The surface (SURFACE) is the package pad. The 2nd and 7th layers are the ground layer and the power layer respectively.
In order to understand the design of the circuit board, first consider the bare board (no device installed) characteristics of the circuit board. According to the rise time Tr=0.17 ns of the high-speed signal on the circuit board, the cutoff frequency can be obtained. After measurement, it can be known that the PAL22V10_SMSOCKETAMDU17 chip concerned on the circuit board will produce an input current change of 0.2 A within 1 ns. The large current change in such a short time will cause the circuit board to resonate in various modes, resulting in uneven voltages in the power layer and the ground layer.
The resonance characteristics of the bare board are simulated in the 3 GHz frequency domain. The specific method is to add a 0.1 Ω resistor between the power supply and the ground on one side of the board, which is equivalent to the VRM effect. A port is added in the middle of the U17 chip to connect the power supply and the ground layer, and the frequency range is 1 MHz to 3 GHz. The Z parameter diagram of the bare board at this time is shown in Figure 1.

As shown in Figure 1, a resonance point is 0.08 GHz. The frequency is swept from 0.08 GHz to 3 GHz. The voltage distribution between some resonance points and the corresponding power supply/ground is shown in Figure 2.

As shown in Figure 2, the circuit board will resonate at many different frequency points. Through simulation, it can be obtained that in the resonant modes of 0.324 GHz and 0.793 GHz, the voltage difference between the power layer and the ground layer at the center of the U17 chip is zero in the former, while it is not zero in the latter.
Devices that generate a large amount of current changes in a short period of time can be placed at the point of zero voltage difference change to avoid low-frequency resonant modes in the circuit board.
Although the layout and placement of devices can help reduce power integrity problems, they cannot solve all problems. First, it is impossible to place all key devices in the center of the circuit board. Usually, the flexibility of device placement is limited; second, there will always be some resonant modes excited at any given location. As shown in Figure 3, the "o" curve shows the resonance phenomenon caused when the chip located in the center of the circuit board draws current from the power plane; the "-" curve represents the response when the chip is placed offset from the center. It can be seen that if the chip is placed offset from the center along a certain coordinate axis, other resonant modes will be excited. The key to successfully designing a circuit board's PDS (power distribution system) is to add decoupling capacitors at the right location to ensure the integrity of the power supply and that the ground bounce noise is small enough over a wide enough frequency range.

In order to ensure the correct operation of high-speed devices, voltage fluctuations should be eliminated and a low-impedance power distribution path should be maintained. To this end, decoupling capacitors need to be added to the circuit board to minimize the noise generated by high-speed signals on the power layer and the ground layer. The number of capacitors, the capacitance of each capacitor, and the appropriate position on the circuit board all need to be strictly defined.
The U17 chip draws 0.2 A of current at the rising edge of 1 ns. At this time, the power supply voltage will temporarily decrease (voltage drop) and the ground plane voltage will temporarily be pulled up (ground bounce). The magnitude of the change depends on the impedance of the circuit board and the decoupling capacitor used to provide current at the chip bias pin.
Since the transient value of the current is 0.2 A, the transient value of the voltage is determined by V=Z×I, where Z is the equivalent impedance from the chip end. Figure 4 shows the impedance distribution diagram of the circuit board used in this article. In order to avoid voltage spikes, the Z value must be lower than a certain threshold value Ztarget in the frequency range from DC to the signal bandwidth. The Ztarget variation depends on the impedance of the circuit board and the decoupling capacitor used to provide current at the chip bias pin. In order to avoid voltage spikes, the Z value must be lower than a certain threshold value in the frequency range from DC to the signal bandwidth. The dotted line in Figure 4 is the target area that the PDS impedance should meet.

In this design, in order to maintain the integrity of the power supply, the power/ground voltage fluctuation must be kept within 5% of the standard value of 3.3 V. Therefore, the noise cannot be greater than 0.05×3.3 V=165 mV. Based on this, the maximum impedance of the PDS can be calculated according to Ohm's law: Ztarget=165 mV/0.2 A=0.825 Ω.

In the design, the fastest signal transition time is 0.17 ns, so the overall design cutoff frequency is 3 GHz. In order to achieve this bandwidth, it is usually necessary to place a lot of high-frequency ceramic capacitors (nF) in the MHz signal area and place larger electrolytic capacitors (?F) in the kHz signal area. From the system design book, it can be seen that the rise time of the U17 chip is about 1 ns, so its operating cutoff frequency is about 500 MHz. Therefore, it is required that within the 500 MHz frequency range, the power supply/ground impedance near the U17 chip is less than 0.825 Ω.
Using SIwave, a port can be placed at the power supply/ground of the IC (U17) chip to calculate the input impedance of the circuit board within the appropriate bandwidth. The simulation shows the influence of the capacitance of the circuit board itself and ignores the low inductive current loop through the power supply. From the simulation results, it can be seen that the impedance increases with the decrease of frequency, but because the loop through the power supply has low impedance, this relationship is not strict.
In order to make the impedance lower than the target impedance of 0.825 Ω at 1 MHz, the capacitance value must be at least 0.18 μF. To this end, it is necessary to first add 6 30 nF capacitor matrices (ESL=0.5 nH, ELR=0.05 Ω). The simulated Z parameters at this time are shown in Figure 5.

Continuing the resonance simulation, the board resonates at f=0.257 GHz. Then, four 10 nF capacitor matrices (ESL=0.3 nH, ELR=0.03 Ω) are added. The simulation parameters at this time are shown in Figure 6.

As shown in Figure 6, the first peak value changes from 180 MHz in Figure 5 to 400 MHz in Figure 6. Then, four decoupling capacitors are added around U17, which are 0.3 nF, 1 nF, 3 nF, and 10 nF capacitor matrices (ESL=0.1 nH, ELR=0.01 Ω). In order to make the simulation consistent with the actual situation, a 0.1 Ω VRM equivalent resistor is added to the top of the board. The simulation Z parameter at this time is shown in Figure 7. As shown in Figure 7, after adding decoupling capacitors, the impedance between power supply/ground becomes very small, and is basically lower than 0.825 Ω within the frequency of 500 MHz. Since capacitors with smaller capacitance have smaller ESL and ESR values, increasing the number of bypass capacitors helps improve its high-frequency characteristics.

2 Using EBG (high impedance electromagnetic surface structure) to suppress SSN
EBG structure is a periodic structure with band-stop characteristics. It can be made of metal, ferromagnetic or ferroelectric materials implanted into the matrix material, or it can be made of various suitable materials arranged periodically. When the EBG structure is used as the PCB substrate, the circuit elements spanning several EBG periodic units will be able to achieve filtering. The EBG structure can be used to integrate filters with very wide stopbands in the microstrip circuit substrate. When it is organically combined with other circuit elements, it can save circuit space.
When the EBG structure is used to suppress SSN, the effect is much better than simply adding decoupling capacitors, especially at high frequencies. Because the increase in frequency requires more decoupling capacitors to be added, which causes some other effects. The use of EBG structure + decoupling capacitors can more effectively provide a larger bandgap width in a higher frequency range, and can meet the minimum impedance requirements of PDS as much as possible at the highest frequency, thereby reducing SSN.
This article will present the simulation results of the PDS design with simple decoupling capacitors and the PDS design with 8×8 square EBG structure plus decoupling capacitors. The first set of data is that a 6×6 capacitor matrix and a 9×9 capacitor matrix are added between two 80 mm×80 mm planar circuit boards, with a capacitance of 10 nF, and their ESL and ESR are ignored. Their Z parameters are tested respectively.
The results show that the characteristic impedance of the 6×6 capacitor matrix is ​​lower than 7 Ω below the frequency of 2 GHz, and the characteristic impedance of the 9×9 capacitor matrix is ​​kept below 7 Ω below the frequency of 3.7 GHz.
The second set of data uses the two structures of the 8×8 EBG structure + 6×6 decoupling capacitor matrix and the 8×8 improved EBG structure + 6×6 decoupling capacitor matrix analyzed above, and the simulation results are obtained.
The results show that the 8×8 EBG + 6×6 decoupling capacitor matrix structure can keep the characteristic impedance below 7 Ω below the frequency of 3.4 GHz, while the 8×8 improved EBG + 6×6 decoupling capacitor matrix structure can keep the characteristic impedance below 7 Ω below the frequency of 4.2 GHz. The results show that the PDS design using the EBG structure is more advantageous than the traditional simple addition of decoupling capacitors.