Realizing LCD Control Based on NIOS II Embedded Processor

With the rapid development of semiconductor technology and computer hardware and software technology, there are more and more ways to control the display of images. This article introduces a new method to control LCD-LQ057Q3DC02 based on NIOS II soft-core processor. In the design, the NIOS II soft-core processor and its "soft" hardware modules related to the display function are customized using FPGA Altera's SOPC Builder to collaboratively implement the software and hardware design of display control. Using SOPC technology, the NIOS II CPU and LCD controller are placed in the same FPGA, which solves the problem that LCD display can only be solved by using a dedicated LCD control chip.

1 LCD selection and main features

The LCD used in this article is SHARP's 5.7-inch LCD-LQ057Q3DC02. It can display 320×240×3 pixels. The input signals include: 18-bit color signal (6 bits for each R, G, and B) data signal, 4 clock signals (CLK, Hsync, Vsync, Enable), and R/L, U/D, and VGA/QVGA mode selection signal lines for horizontal display mode and vertical display mode.


In fact, LCD-LQ057Q3DC02 is a line-by-line scanning device. It always starts scanning from the upper left corner of the screen, first scans a line (320 pixels) horizontally to the rightmost, then returns to the leftmost, changes to the next line, and continues scanning. Until the bottom of the screen is scanned (a total of 240 lines), a frame of the image is scanned, and then returns to the leftmost to start scanning the next frame.

2 Avalon Stream Mode LCD Controller Design

The LCD real-time image display control method implemented in this article adopts the DMA data transmission method. During the design, a DMA transfer channel is established between the streaming mode LCD controller and SDRAM using the DMA controller, allowing the hardware to automatically read the pixel information, and the NIOS II processor can update the LCD image by simply operating the corresponding blocks in the SDRAM.

2.1 Composition of the Avalon streaming mode controller

The Avalon bus specification must be followed when designing Avalon streaming mode peripherals. In actual design, the hardware structure of the Avalon streaming mode LCD controller designed by the author is shown in Figure 1. The controller consists of the following three parts: LCD interface controller, FIFO memory, and Avalon Streaming Port interface.

2.2 LCD display control flow

For LCD-LQ057Q3DC02, to achieve normal LCD display, the corresponding control signals must be correctly configured, especially the line synchronization (LCD_Hsync) and field synchronization (LCD_Vsync) must be synchronized with the image data taken from the SDRAM memory, otherwise, the image will not be reproduced normally. The control timing flow of line synchronization and field synchronization for LCD control is shown in Figure 2.

2.3 LCD controller file composition and part of the code

There are three module files corresponding to the LCD controller hardware, namely: LCD_interface.vhd, LCD_pixel_fifo.v and LCD_controller_stream.v. LCD_controller_stream.v is the top-level module, which also contains the Avalon Streaming Port interface timing part. LCD_pixel_fifo.v can be directly generated through the macro module in QuartusII. After the above three files are generated, you can select the System->Add Interface to User Logic command in SOPC Builder to open the Interface to User Logic dialog box and select the bus type as Avalon Memory Slave, because the LCD controller working in streaming mode can be regarded as a memory (FIFO type), and the DMA setting from memory (FIFO) to memory (SDRAM) can be realized by adding a DMA controller. The following is a partial program of the LCD interface.

ENTITY LCD_interface IS
PORT(
reset :IN std_logic;
lcd_clk :IN std_logic;
Wrdata :IN std_logic_vector(17 downto 0);
hsync :OUT std_logic;
vsync :OUT std_logic;
enable :OUT std_logic;
lcd_R/L :OUT std_logic;
lcd_U/D :OUT std_logic;
sel_VGA_QVGA :OUT st d_logic;
RGB :OUT std_logic_vector(17 downto 0);
end_of_picture :OUT std_logic);
END LCD_interface;
ARCHITECTURE trans OF LCD_interface IS
process(lcd_clk) begin
if(rising_edge(lcd_clk)) then
if(hcnt<400) then
hcnt<=hcnt+1;
else end if ; k
) begin if(rising_edge(lcd_clk)) then if ((hcnt>= 320+20 +20 ) and (hcnt<320+20 +20+40)) then hs< =0 ; else hs<=1; end if; end if ; end process;--generate horizontal synchronization pulse process ( vcnt ) begin if((vcnt>=240+6+6)and(vcnt<240+6+6+10)) then VS<=0; else vs<=1; end if; end process;--Generate field synchronization pulseprocess (lcd_clk) begin if(rising_edge(lcd_clk)) then if(hcnt<320 and vcnt<240)and(hcnt>20 and vcnt>6) then en<=1; else en<=0; end if; end if; end process;--Generate display enable control signalprocess (led_clk)begin if(rising_edge(lcd_clk))then if(hcnt<320 and vcnt<240)then RGB<=Wdata; else RGB<=(others=>0); end if; end if; end process;--Pixel output and blankingprocess (lcd_clk)begin if(rising_edge(lcd_clk))then if((vcnt=320+1)and(hcnt=0))then



















































end_of_picture<=1;
else
end_of_picture<=0;
end if;
end if;
end process;--One frame transmission is completedEND
ARCHITECTURE trans;

3 DMA control process and experimental conclusion

3.1 Program flow under DMA transmission mode

The use of this solution to realize LCD display has been verified in a certain area array CCD acquisition system. In the actual system, this part mainly realizes the dynamic display of the image data collected by the area array CCD image sensor. In the actual acquisition control system, two DMAs are selected, one for image data acquisition and the other for image reproduction after acquisition. Only the corresponding modules under the display DMA transmission control mode are introduced in this article. In the actual system, the image data is collected from the area array CCD image sensor to SDRAM in DMA control mode, and the collected image data is displayed from SDRAM to LCD. The DMA control process in the actual system is shown in Figure 3.

3.2 Experimental conclusion

According to Figure 3, the image data of the area array CCD collected is stored in SDRAM. The image data extracted at a certain ratio is synthesized into an 18-bit RGB image signal in SDRAM. Then, under the control of the NIOS II processor and display DMA, a complete frame of the image is displayed on the LCD. The actual control display result is shown in Figure 4.

4 Conclusion

Using NIOS II as a solution for controlling LCD with FPGA embedded processor can easily realize DMA transmission and control of image data. The system can selectively customize the corresponding modules according to actual needs, making the system more flexible. At the same time, since the LCD control is realized by using "soft" hardware, the purpose of improving hardware functions can be achieved by constantly changing the "software" during the debugging process.