Implementation of a High-Efficiency Buck/Boost Converter Based on Inverse SEPIC

There is a growing demand in many markets for high-efficiency, non-inverting DC-DC converters that can operate in either buck or boost mode, that is, step down or step up the input voltage to the desired regulated voltage, with minimal cost and component count. The inverse SEPIC (single-ended primary inductor converter), also known as the Zeta converter, has many features that support this function (Figure 1). An analysis of its operation and implementation using the ADP1877 dual-channel synchronous switching controller will provide insights into its useful features in this application.

The primary switch QH1 and the secondary switch QL1 operate in anti-phase. During the on-time, QH1 is on and QL1 is off. Current flows along two paths, as shown in Figure 2. The first path is from the input through the primary switch, the energy transfer capacitor (CBLK2), the output inductor (L1B), and the load, and finally back to the input through ground. The second path is from the input through the primary switch, the ground reference inductor (L1A), and ground back to the input.

Figure 2. Current flow diagram; QH1 is closed, QL1 is open.

During the off period, the switch positions are reversed. QL1 is on and QH1 is off. The input capacitor (CIN) is disconnected, but current continues to flow through the inductor along two paths, as shown in Figure 3. The first path is from the output inductor through the load, ground, and the secondary switch back to the output inductor. The second path is from the ground-referenced inductor through the energy transfer capacitor, the secondary switch, and back to the ground-referenced inductor.

Figure 3. Energy transfer diagram; QL1 is closed, QH1 is open

Applying the principles of inductor volt-second balance and capacitor charge balance, the balanced DC conversion ratio specified by Equation 1 can be obtained, where D is the duty cycle of the converter (the on-time portion of a cycle).

The above equation shows that if the duty cycle is greater than 0.5, the output will get a higher regulated voltage (boost); if the duty cycle is less than 0.5, the regulated voltage will be lower (buck). In addition, other relevant results can be analyzed: in a lossless system, the steady-state voltage on the energy transfer capacitor (CBLK2) is equal to VOUT; the DC current flowing through the output inductor (L1B) is equal to IOUT; the DC current flowing through the ground reference inductor (L1A) is equal to IOUT × VOUT/VIN. The energy transfer capacitor also provides DC isolation from VIN to VOUT. This feature is useful when there is a risk of output short circuit.

The analysis also shows that the output current in the inverse SEPIC is continuous, which results in lower peak-to-peak output voltage ripple for a given output capacitor impedance. This allows the use of smaller, less expensive output capacitors, compared to the larger, more expensive capacitors required to achieve the same ripple requirement in discontinuous output current topologies.

Typically, the secondary switch (QL1) is a unidirectional power diode, which limits the peak efficiency of this topology. However, by using one channel of the Analog Devices ADP1877 dual-channel synchronous switch controller (see Appendix) and using a bidirectional MOSFET as the secondary switch, an inverse SEPIC in a “fully synchronous configuration” can be designed. In this way, the peak efficiency will be greatly improved while reducing the size and cost of the converter for output currents greater than 1 A.

Figure 4 shows the power stage of a fully synchronous inverse SEPIC configuration, implemented using the ADP1877 and requiring only three small, inexpensive additional components (CBLK1, DDRV, and RDRV) that consume negligible power.

Figure 4. Synchronous inverse SEPIC power stage implemented using Channel 1 of the ADP1877.

The ideal steady-state waveforms for the inverse SEPIC are shown in Figure 5. The channel 1 switch node SW1 (see Appendix Figure A) switches between VIN + VOUT (during the on-time) and 0 V (during the off-time). The charge pump capacitor CBST, connected to SW1, applies a voltage of approximately VIN + VOUT + 5 V to the bootstrap upper rail of the high-side internal driver (BST1 pin) and the output of the high-side driver (DH1 pin) during the on-time, thereby enhancing the primary floating N-channel MOSFET switch QH1. The clamp diode DDRV, ensures that the voltage on CBLK1 during steady-state output is approximately VOUT + VFWD(DDRV), which is referenced to the voltage from the DH1 pin of the ADP1877 to the gate of QH1. During the off-time, when the X-node voltage is approximately –VOUT, the voltage on CBLK1 prevents the primary switch from developing a gate-to-source voltage above its threshold.

Figure 5. Ideal waveforms of synchronous inverse SEPIC (ignoring dead time)

The ADP1877 has a pulse skipping mode. When enabled, it can reduce the switching rate and only provide enough energy to the output to keep the output voltage stable, thereby improving the efficiency at light loads and greatly reducing gate charge and switching losses. This mode can be enabled in both synchronous inverse SEPIC and synchronous buck topologies. The DC-DC conversion circuit shown in Figure 4 only requires one channel of the dual-channel ADP1877, so the other channel can be used in either topology.

Inductor Coupling and Energy Transfer Capacitors
In Figure 4, power inductors L1A and L1B are shown coupled to each other. In this topology, the purpose of the coupled inductors is to reduce the ripple of the output voltage and inductor current, and to increase the maximum possible closed-loop bandwidth, as will be explained in the next section.

Although these inductors are coupled to each other, it is not desirable to couple them so tightly that a large amount of energy from one winding is transferred through the core to the other winding. To avoid this, the leakage inductance (LLKG) of the coupled inductors must be calculated and the energy transfer capacitor (CBLK2) must be selected so that the magnitude of its complex impedance is 1/10 of the complex series impedance of the leakage inductance and the single winding resistance (DCR), as shown in Equations 2, 3, and 4. Designing the circuit according to this relationship can minimize the energy transferred by the coupled core. The leakage inductance can be calculated based on the coupling coefficient provided in the coupled inductor data sheet.

A turns ratio of 1:1 is preferred because each winding requires only half the inductance of a discrete inductor for a given level of output voltage ripple. 1 Turns ratios other than 1:1 can be used, but the results will not be accurately described by the equations in this article.

Small Signal Analysis and Loop Compensation
A complete small signal analysis of the inverse SEPIC converter is beyond the scope of this article, however, it will be more academically sound if the following guidelines are followed.

First, many complex impedance interactions at the resonant frequency (fRES) must be calculated to find an upper limit on the target crossover frequency. When the inductor is decoupled, this frequency decreases, resulting in a significant reduction in the maximum possible closed-loop bandwidth.

At this frequency, there can be 300° or more of “high-Q” phase lag. To avoid problems with the converter having too little phase margin over the entire load range, the target crossover frequency (fUNITY) should be 1/10 of fRES. The damping of this resonance is primarily determined by the output load resistance and the DC resistance of the coupled inductor. To a lesser extent, the damping also depends on the equivalent series resistance (ESR) of the energy transfer capacitor and the on-resistance of the power MOSFETs (QHl and QL1). Therefore, it is not surprising that the characteristics of the closed-loop transfer function change significantly at this frequency when the output load resistance changes.

The coupling coefficient is not usually a parameter that can be precisely controlled, so the target crossover frequency should be set to a value 10 times lower than fRES (assuming fRES is less than the switching frequency, fSW). When fUNITY is set appropriately, standard “Type II” compensation can be used—two poles and one zero.

Figure 6 shows the equivalent circuit of the ADP1877 feedback loop in a synchronous inverse SEPIC buck-boost topology. The upper box contains the power stage and current loop, and the lower box contains the voltage feedback loop and compensation circuitry.

Figure 6. ADP1877 power stage and compensation scheme with internal current sensing I loop in synchronous inverse SEPIC topology.

The compensation component values ​​in the lower box can be calculated using the following formula:

The transconductance GCS of the converter is calculated using the following formula:

COUT is the output capacitance of the converter. ESR is the equivalent series resistance of the output capacitance. RLOAD is the minimum output load resistance. ACS is the current sense gain, which can be selected in discrete steps from 3 V/V to 24 V/V for the ADP1877. Gm is the transconductance of the error amplifier, which is 550 μs for the ADP1877. VREF is the reference voltage connected to the positive input of the error amplifier, which is 0.6 V for the ADP1877.

GCS is a frequency-independent gain term that varies with the enhanced secondary switch resistance, RDS(ON). The highest crossover frequency is expected to occur when this resistance and duty cycle, D, are lowest.

To ensure that the compensation clamp voltage is not reached at maximum output current, the current sense gain (ACS) should be selected to a maximum value that satisfies the following conditions:

Where ∆IL is the peak-to-peak inductor ripple current.

If there is too much slope compensation, the equations here will become less accurate: the DC gain will be reduced and the frequency location of the dominant pole caused by the output filter will increase.

Slope Compensation
For the synchronous inverse SEPIC implemented with the ADP1877, the subharmonic oscillation phenomenon in the current-mode controller 2 must be considered.

By setting RRAMP as follows, the quality factor of the sampling pole can be set to unity, thus preventing subharmonic oscillations3 (assuming fUNITY is set appropriately).

It is important to note that as the enhanced secondary switch resistance RDS(ON) decreases, the Q of the sampling pole also decreases. If this factor, along with other relevant tolerances, results in a Q less than 0.25, simulations should be performed to ensure that the converter does not have too much slope compensation and is not too biased toward voltage mode given the tolerances. The value of RRAMP must be such that the current at the RAMP pin of the ADP1877 is in the range of 6 μA to 200 μA, which is calculated as follows:

Power device stress
From the current flow diagrams in Figures 2 and 3, it can be seen that the power MOSFET has to carry the sum of the inductor current after it is turned on. Therefore, the DC component of the current flowing through the two switches is:

If the inductor coupling ratio is 1:1, the AC component of the current flowing through the two switches is:

Knowing these values, the RMS current through each switch can be quickly calculated. These values, along with the RDS(ON)MAX of the selected MOSFET, ensure that the MOSFET is thermally stable while the power dissipation is low enough to meet the efficiency requirements.

Figure 7. Ideal current waveform of synchronous inverse SEPIC (ignore dead time)

Precisely calculating the switching losses of the primary switch is beyond the scope of this article, but it should be noted that the voltage across the MOSFET swings from approximately ~VIN + VOUT to ~0 V when changing from a high-impedance state to a low-impedance state, and the current through the switch swings from 0 A to IOUT[1/(1 – D)]. With such high swings, switching losses can be the dominant loss, which is something to keep in mind when selecting a MOSFET; for MOSFETs, the reverse transfer capacitance (CRSS) is inversely proportional to RDS(ON).

The drain-source breakdown voltage (BVDSS) of both the primary and secondary switches must be greater than the sum of the input and output voltages (see Figure 5).

The peak-to-peak output voltage ripple (∆VRIPPLE) can be approximated by the following equation:

The rms current flowing through the output capacitor (I rms COUT) is:

The peak-to-peak inductor current (∆IL) expressed in Equation 12 depends on the input voltage, so it is important to ensure that when this parameter is changed, the output voltage ripple does not exceed the specified value and the rms current flowing through the output capacitor does not exceed its rated value.

For a synchronous inverse SEPIC implemented with the ADP1877, the sum of the input voltage and the output voltage must not exceed 14.5 V because the charge pump capacitor is connected to the switch node and its voltage reaches VIN + VOUT when the primary switch is on.

Lab Results
Figure 8 shows the efficiency of the synchronous inverse SEPIC versus load current for 5 V output and 3 V and 5.5 V inputs. This is a common case for applications that need to switch between 3.3 V and 5.0 V input rails, or when the input voltage is adjusted in real time to optimize system efficiency. With a 1 A to 2 A load, the converter's efficiency is over 90% regardless of whether the input voltage is above or below the output voltage.

Figure 8. Efficiency vs. load current

The bill of materials for the power devices associated with Figure 8 is shown in Table 1, using only common off-the-shelf components. A comparable asynchronous design using an industry-leading Schottky diode with a low forward voltage drop in place of QL1 is nearly 10% less efficient at full load for both input voltages. In addition, the asynchronous design is larger, more expensive, and may require an expensive heat sink.

Table 1. Power Devices