1 Hardware Description and Working Principle
The main hardware includes: PIC12C508 microcontroller, 2 74HC595 shift registers, 8 LED digital tubes, and 8 current limiting resistors of about 220 Ω.
1.1 Introduction to PIC12C508
PIC12C508 is a CMOS microcontroller developed by MICROCHIP with low price, low power consumption, high performance, 8 bits, and full static. It adopts RISC structure and has a wide range of applications, especially for portable electronic products.
The pin diagram of PIC12C508 (see Figure 1) is as follows:
GP0: bidirectional input/output port/serial programming data port;
GP1: bidirectional input/output port/serial programming clock port;
GP2: bidirectional I/O port;
GP3: input port;
GP4: bidirectional I/O port;
GP5: bidirectional I/O port.
1.2 Introduction to 74HC595
74HC595 has 8-bit shift registers, 1 memory and three-state output function. The shift register is serial input and 8-bit parallel (or serial) output. The shift register and memory are respectively input and shifted by clock and data at the rising edge of SR-CLK: Q0→Q1→Q2→…→Q7, and enter the storage register at the rising edge of RCLK. When E is low, the data of the storage register is output to the bus. The functions of the 74HC595 pin diagram (see Figure 2) are as follows:
Q0~Q7: parallel data output terminal;
Q7': cascade output terminal;
SRCLK: shift register clock pulse input terminal;
RCLK: storage register clock pulse input terminal;
SER: serial data input terminal;
E: output valid (low level);
SRCLR: master reset (low level).
1.3 Hardware circuit design
In the circuit, two 74HC595s, one as segment code driver A and the other as bit code driver B, are connected in cascade. The GP0, GP1 and GP2 ports of the single-chip microcomputer PIC12C508 are analog data output ports and clock output ports. The serial data input port (SER) and shift register clock port (SRCLK) of segment code driver A are connected to the GP0 and GP1 ports of 12C508 respectively, and the storage register clock port (RCLK) is connected to GP2. The SER and SRCLK ports of bit code driver B are connected to the cascade output port (Q7') of segment code driver A and the GP1 port of 12C508 respectively, and the RCLK port is connected to GP2. At the same time, the E terminals of the two 74HC595s are grounded (see Figure 3).
During the display process, the segment code value of the character to be displayed is determined by the decoding table, and its bit code value is determined to be FEH (1111 1110) according to the display position of the character in the LED (assuming it is the lowest bit). First, the bit code value is sent to the segment code driver A under the action of the SR-CLK pulse; then the character segment code value is taken and also sent to the segment code driver A. At this time, the bit code value has been sent to the bit code driver B through the cascade terminal Q7'. Then, let GP2 output a rising edge, so that the value in the shift register is output to the storage register, and then output from the 8 parallel output terminals. After a delay of 2 ms, the character can be displayed at the predetermined position. If it is required that the bit code becomes FDH (1111 1101) when displaying the lower two bits, then the segment code value of the second character is decoded and the above process is repeated. In this way, the display program is called cyclically in the main program, and the segment code and bit code are sent alternately, so that the LED can achieve the ideal display effect.
2 Program flow and writing
The main program flow chart is shown in Figure 4. The following program realizes the display of numbers 0 to 7:
3 Conclusion
This paper introduces a new type of LED display circuit, which adopts serial mode, greatly saves the I/O port of single-chip computer, and the chip used is small in size and low in price. The software decoding method increases the amount of displayed information and simplifies the hardware circuit. Therefore, this module is particularly suitable for low-cost portable systems.
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