Power supply and PDS design for complex circuit systems

Modern large integrated circuits, such as CPUs and large FPGAs, often consume currents ranging from several amperes to tens of amperes, and some complex systems have a wide variety of power supplies. Therefore, whether the power supply system is designed reasonably is often the key to whether the system can work stably. The design of the power supply system should include three aspects: power supply evaluation, power supply circuit design, and power distribution system (PDS). This article discusses the general design methods and ideas for these three aspects.

1. Power supply evaluation
Evaluating the power supply is the first and most important step in designing a power supply system, which determines the success or failure of the power supply design. When designing the power supply, the block diagram design of the entire system should have been completed and the important IC chips should have been basically selected. At this time, we need to refer to the data sheet to obtain the operating voltage and current consumption of each IC, and draw the following table:
Table 1, IC power supply evaluation table

1. Power supply type
Power supply types can be divided into two categories: analog and digital. Analog power supply refers to the power supply for analog circuits such as PLL, ADC/DAC; while digital power supply mainly powers digital circuits. It can be divided into core power supply (mainly for the core logic circuit of integrated circuits, such as FPGA core power and voltage source) and I/O power supply (mainly for I/O interface). Modern large IC power supply generally uses separate core voltage and I/O power supply.
2. Voltage value
Voltage value generally includes minimum, typical and maximum values. Generally, the circuit power supply designed should work at the typical working voltage, and the power supply fluctuation range should not exceed the minimum and maximum range.
3. Current
When designing the power supply, the current value should consider the worst case. For example, the current of a large FPGA system may vary a lot depending on the number of logic gates used; when designing the power supply circuit, a certain design margin should be provided based on the maximum current evaluated.

4. Power consumption
The purpose of calculating the power consumption of each power supply is to distribute the power supply tree more reasonably. Please refer to the power supply tree section.

After obtaining the power parameters of each IC, we need to draw a statistical table like the one below. This step is to prepare for the design of the power circuit and planning of the power Tree.

2. Power supply circuit design
1. Analog
power supply Analog power supplies are often used to power analog circuits such as PLL, ADC/DAC, current source, etc. They are characterized by low current, generally between tens of mA and hundreds of mA, and are sensitive to power supply ripple. Therefore, the design of analog power supply circuits often chooses LDO, which we call linear power supply; and LC or ferrite should be used to filter the power supply at the IC pin input to further reduce the power supply ripple. Its typical principle is shown in Figure 1:

Figure 1

2. Digital power
supply Digital power supply is generally used to power logic circuits. They often require a lower voltage but a higher current. For example, the core power supply of a modern X86 CPU is generally around 1V, but the supply current can reach tens of amps. And due to the switching of the power saving state inside the CPU, the current changes greatly (the working current in the most power saving and full speed states may differ by dozens of times).

The design of this type of power supply generally uses a digitally modulated switching power supply. This type of power supply generally consists of a PWM controller and an external output MOS tube, a BOOT circuit, a feedback network, and an LC filter circuit; in addition, some LDO power supplies that can provide larger currents can be selected. For ultra-large current power supply, it is also necessary to consider using multiple power supplies. The following figure is a schematic diagram of a single-phase PWM power supply circuit:

Figure 2
3. Drawing of the power supply tree
After selecting the power supply chip of the power supply, you can start drawing the power supply tree. Let's take a typical motherboard power supply circuit as an example. First, the external power supply used by the motherboard comes from a 350W power supply, which is divided into 12V, 5V, 5Vsus and 3.3V inputs, and the power supplies used on the motherboard are 12V, 5V (standby voltage 5Vsus), 3.3V (standby voltage 3.3Vsus), CPU core voltage Vcore_cpu, CPU PLL analog power supply, front-end bus power supply, memory 1.8V power supply (standby voltage 1.8Vsus), etc. In fact, there are many other power supplies on a motherboard, such as chipset power supply, etc. We need to reasonably allocate each power supply to ensure that the total power at the end of each power supply path does not exceed the power supply capacity of the front-end power supply. In the end, we should draw a power supply tree similar to that shown in Figure 3 (just a schematic diagram):

Figure 3
Of course, for a simple system design the power supply may not be so complex.

4. Power supply power-on timing
For more complex systems, after drawing the power supply tree, we should draw a specific and clear power-on timing diagram based on the power supply power-on sequence and system reset signal requirements, as shown in Figure 4. And use this power-on timing diagram to guide the power-on sequence of the power supply IC during power supply design. Figure

4

3. PDS system design
The most important part of PDS system design is the selection and distribution of decoupling and bypass capacitors. Many people think that the functions of bypass and decoupling are the same, but in fact they are different.

1. Working principle of decoupling and bypass capacitors
1) The bypass model is shown in the figure

When high-frequency current fluctuations occur inside the IC, such as the switching of I/O or gates, these high-frequency transient current changes will cause high-frequency current fluctuations if they draw current from the power supply. The internal resistance of the current source and the power supply line are inductive impedance L at high frequencies. The higher the frequency, the greater the impedance, which causes a larger voltage drop at the IC power pin. Therefore, a capacitor Cbp is placed close to the IC power pin to provide transient current for the IC. When the transient current changes, the IC pin will draw current from the low-impedance capacitor C (theoretically, the current can flow from the power line and the capacitor, but the capacitor impedance is low, so the current will mainly flow along the capacitor). After the capacitor voltage drops, the charge will be replenished from the power line. In essence, the role of the bypass capacitor is to reduce transient (high-frequency) current fluctuations on the power line. The bypass capacitor provides charge for high-frequency charging and discharging, so its ESR and ESL (including the lead inductance to the power pin) should be as low as possible and as close to the power pin as possible. Commonly used bypass capacitors are small-capacity (0.1uF, 0.01uF, etc.) ceramic capacitors.

2) Decoupling model is shown

in the figure. Circuit IC1 will inevitably generate some noise or current fluctuations on the power line (mainly in the lower frequency band, because high-frequency current fluctuations can be eliminated by its bypass capacitor). If a power supply supplies power to multiple IC modules at the same time, the noise on one IC will be transmitted to another IC circuit. In order to reduce the noise coupling between modules, capacitor Cdec is placed. It and the inductor on the power line form an LC low-pass filter circuit. When the noise (from another circuit module, or from the power supply itself, such as the output voltage of the switching power supply itself contains a lot of noise) is transmitted along the power line to a certain IC, it will be eliminated by this LC low-pass filter. In essence, the role of the decoupling capacitor is to prevent the power supply noise from being transmitted from one circuit module to another. The decoupling capacitor needs to filter out the lower-frequency noise on the power line, so the cutoff frequency of the LC low-pass filter should be lower. At the same time, the Cdec capacitor also provides charge and stabilizes the voltage for the subsequent circuit (including many bypass capacitors). Therefore, the capacitor Cdec has a large capacity, and a large-capacity (tens to hundreds of uF) tan capacitor is often used.

2. Size and location of decoupling and bypass capacitors
The ultimate goal of decoupling and bypassing is to generate a stable voltage at the power pin of the IC. They both require to be as close to the power pin of the IC as possible. In actual systems, it is sometimes not necessary to deliberately distinguish between decoupling capacitors and bypass capacitors, and they are collectively referred to as decoupling capacitors.
1) Small-capacity ceramic capacitors (generally 0.01uF~0.22uF) are used as bypass capacitors. The principle of placement is to minimize ESL. Generally, 0402 packages are used and should be placed closest to the power pins. Now a large number of high-density integrated circuits use BGA packages. All of its pins are at the bottom of the chip, connected to the top layer pad of the PCB through the pin ball, and the power bus or plane generally extends to the power pin at the bottom of the chip package through the Via via. Therefore, the position closest to the power pin is the back of the PCB at the bottom of the chip package, and the capacitor PAD is best connected directly to the via via. Some chips will also have capacitors directly soldered on the package substrate, so that the number of bypass capacitors on the PCB can be reduced.
2) Large-capacity decoupling capacitors (generally >33uF) generally have larger packages and cannot be placed very close to the pins of the chip. However, this type of capacitor is used to filter out lower-frequency noise and is not particularly sensitive to the placement position, so the most suitable position may be at the edge of the chip, close to the chip.
3) Sometimes, ceramic capacitors with a capacity of several uF (2.2uF, etc.) are placed between the decoupling Cdec and the bypass capacitor Cbp as an intermediate stage. It is generally believed that they are used to filter out some intermediate-frequency noise and provide charge for nearby bypass capacitors. These capacitors generally use 0805 packages and should also be placed as close to the power pins as possible.
When selecting a specific capacitor, you must also consider factors such as the size of its ESR, the frequency of the noise, and determine the number of capacitors. Sometimes, appropriate simulation simulation is needed to assist in the design.

3. PDS distribution design example
Example 1
The power pins of the BGA packaged chip are concentrated near the center of the chip. The power is connected to the center of the chip in a bus-like manner. The possible capacitor layout is shown in the figure. The upper and lower sides are small capacitors of 0.1uF and 0.01uF, the center is a 2.2uF ceramic capacitor, and the tank capacitor is placed at the edge of the chip. The specific layout and the position of the vias need to be adjusted according to the distribution of the power pins. In principle, it should be paired with one large and one (or several) small ones.

Example 2
uses the power plane method. The decoupling capacitor is placed at the edge of the chip near IC2. IC1/IC3 are other chips that use the power supply. The center of IC2 is a small capacitor and a medium-capacity ceramic capacitor.