Design of large LED display system based on S3C44B0X

Large-scale LED display systems have been widely used in various indoor and outdoor occasions, but because they mostly use multi-machine systems, the system cost and the complexity of software and hardware design are increased. When a multi-machine system is working, it is essentially equivalent to a computer system with a high bus width. Its technical difficulties are as follows:

◆ There are tens of thousands of pixels on a large LED display screen. As the display area increases, the circuit structure also increases.

◆ In order to ensure a certain display quality, the frame rate should be above 30 frames/s. For a 512×252 monochrome LED screen, the data transmission volume per second is at least 480 KB or more. For color screens and occasions with high display quality, the data transmission volume will also increase by integer multiples.

◆ When the LED screen is located outdoors, the communication between the upper and lower computers may be over 100 meters or even 1,000 meters, requiring fast and reliable communication speed.

In view of the above two technical difficulties, in order to use a single CPU system instead of a multi-machine system to control a large LED display system, the following coping strategies are adopted:

◆ Large-scale LED screens are composed of universal display modules, which have good versatility and embeddability.

◆Using the 16-bit parallel bus data transmission method, to display the display module at the corresponding position, the column latch unit on the module can be accurately selected, so that the horizontally cascaded LED display module can be regarded as a continuous storage unit.

◆Using the DMA controller inside the S3C44BOX for data transmission and control, it saves the CPU instruction fetch and translation time for data transmission using instructions, as well as the software overhead of counting, comparing, jumping, etc. for data transmission using instructions, so that data transmission can be completed in continuous read and write operations, improving the speed and efficiency of data transmission.

1 Hardware structure and principle

Large-scale LED display systems are generally divided into two parts: the main control board and the display driver module.

1.1 Display module

Nowadays, large-scale LED display systems use the characteristics of human vision to use progressive scanning and column driving to save hardware expenses. This system uses 1/16 progressive scanning, so the entire large LED screen is divided into 16 rows of the same name. The schematic diagram of the display module is shown in Figure 1.



Each display module is a 64×32 small dot matrix screen, divided into two parts, 16 rows in the upper and lower parts, and each part has 8 groups of column data latches. The upper and lower parts reuse a 4-16 decoder U1, which is driven by 1/16 line-by-line scanning display, and 16 sets of column driver latches are required to latch the column display data. When using the parallel bus data transmission method, a 4-16 decoder U2 is required to enable the column latch. When refreshing the dot matrix, two-level latches are required to latch the column display data, otherwise the display tailing phenomenon will occur. The data being displayed this time is stored in the second-level latch. The main control board refreshes the column data of the next row of data to be displayed by the first-level latch on the screen. After the data to be displayed in the next row is transmitted, it is latched to the second-level latch output and driven to drive the next row of display. Using the parallel bus method, the second-level latch is still more economical than the solution of serial data transmission and then converted to parallel output.

When the display modules are horizontally cascaded, the idea of ​​staggered cascading is used to make it have good versatility and embeddability. As shown in Figure 1, the strobe line will be dislocated once at each level and passed to the next level, always making the first strobe line BLK_EN0 the enable control line of the first-level column latch decoder, so that n strobe lines can sequentially select n-level horizontal cascade modules. In this way, the same display module can be used to arbitrarily combine into a horizontal cascade strip screen.

Using the idea of ​​dislocation cascading, the decoder U2 of the first-level latch on the horizontal cascade display module can be sequentially selected, and the decoder can sequentially select the first-level column data latch, so that the first-level column data latch on the horizontal cascade screen can be regarded as a continuous storage unit, which is the basis for using DMA parallel data transmission control.

Interface design between the main control circuit and the LED screen #e#

1.2 Interface design of main control circuit and LED screen

This display system uses S3C44BOX based on ARM7TDMI core and with internal DMA controller as the main controller, so that it works in ARM state and uses 16-bit bus. Since the LED screen is virtually regarded as a continuous storage unit, the address space 0x2000000~Ox4000000 is allocated to it.

The main control circuit and LED screen interface should be able to achieve the following functions:

◆ Select the display module at any position and the first-level column data latch on the module. Accurately latch the dot matrix code to be displayed at this position, and after the data of the first-level column data latch is refreshed, the refreshed data can be latched into the second-level column data latch and output.

◆ Can control the selection drive of one of the 16 rows of the same name for line-by-line scanning display.

◆ Realize the logic level conversion from 3.3 V of the main control chip to 5V of the LED screen.

The schematic diagram of the main control board and LED screen interface circuit is shown in Figure 2.



The structure of a large LED screen can be divided into vertical cascade and horizontal cascade. This structure is similar to a three-dimensional array. Assume a three-dimensional array LED[i][j][k], where:

i=0, 1, 2, ..., m represents the serial number

of the vertical cascade level of the LED screen. j=0, 1, 2, ..., n represents the serial number of the horizontal cascade level of the LED screen.

k=0, 1, 2, ..., 16 represents the serial number of the 16 first-level column data latches on the display module.

Since the system uses a 16-bit parallel bus data transmission method and regards the LED screen as a continuous storage unit, A[4:1] is used as the decoding input of the first-level column data latch decoder (U2 in Figure 1) on the display module, which is the k variable of the three-dimensional array; A[8:5] is used as the decoding input of the decoder (U7 in Figure 2) for selecting the horizontal cascade display module, which is the j variable of the three-dimensional array; since the LED screen must have good flexibility and the technical requirements of the dot matrix code storage order required by DMA data transmission, the vertical cascade level selection does not meet the conditions for using the address bus decoding selection, so PG[2:0] of S3C44BOX is used as the decoding input of the vertical cascade level selection decoder, which is the i variable of the three-dimensional array.

Since the status on the address and data buses is constantly changing, the address and data signals should be latched when writing to the LED screen. U2, U3 and U4 are used on the main control board to latch the status of the address and data buses when writing to the LED. The LED screen is assigned the first address of Ox2000000. When writing to it, the nGCSl and nWE pins of S3C44BOX will appear an effective low level with a programmable control delay. nGCSl is used as the latch enable control signal of U2, U3 and U4 through a NOT gate, ensuring that the signals on the address and data bus are latched only when the LED screen is accessed. nWE is used as the latch enable control signal of the first-level column data latch (U3~U19 in Figure 1) at the screen end through a NOT gate, ensuring that the refresh data is latched only when it appears stably at the column data latch input end. PCI0 of S3C44BOX is the latch enable control signal line of all second-level latches at the screen end (U20~U35 in Figure 1); PC[3:O] of S3C44BOX is the decoding input of the 16-row driver decoder (U1 in Figure 1). Since the main control board only needs to control the output of the LED screen during data transmission, and no signal feedback is required, the interface circuit uses a cheap 5V powered HCT circuit chip solution to meet the logic level conversion from 3.3V of the main control chip to 5V of the LED screen.

When DMA transmits data, the DMA write operation is more concerned, and the timing is shown in Figure 3. At t1, the DMA write operation starts, and the address and refresh data of the corresponding position of the LED screen appear on the address and data bus; at t2, the nGCS1 pin appears an effective low level, and the data on the address and data bus is latched into U2~U4 and output; at t3, the nWE pin appears an effective low level, and the output data of U2~U4 is latched into the first-level column data latch at the screen end and output. In this way, the main controller completes a column data refresh.

2 Software Design

2.1 LED Screen Display Program Design

Due to the use of the internal DMA controller of S3C44B0X for data transmission and control, the display program is greatly simplified, and the program flow is shown in Figure 4. The transmission of the dot matrix code is completed by the DMA controller. Before starting the DMA data transmission, you only need to assign the first address of the dot matrix code, the first address of the LED screen and the value of the transmission data volume to the corresponding control word, and then start the DMA operation. After completing the transmission of all the dot matrix codes of the same name row, the refreshed data is latched to the output of the second-level column data latch, and the same name row is driven to display. In this way, after 16 rows of the same name are displayed in a loop, a frame of dot matrix display is completed.



2.2 Dot Matrix Sorting

Due to the circuit structure of the LED display module and the use of 16-bit parallel bus and DMA data transmission technology, the order of dot matrix code during display needs to meet the following requirements:

①16-bit parallel bus data transmission, that is, one DMA write operation transmits two bytes of dot matrix code, and the low-order and high-order bytes are respectively transmitted to the same-name row and column data latches of two adjacent vertical cascade modules, so the same-name row and column dot matrix codes of adjacent vertical cascade modules should be stored continuously.

②Due to the decoding selection circuit structure of the first-level column data latch of the display module and the DMA data transmission requirements, the same-name row dot matrix of the upper and lower parts of the same display module should be stored continuously in sequence according to the selection order of the column data latch.

③A series of horizontal cascade levels of two adjacent vertical cascade levels should be sorted according to the principles of ① and ②

for dot matrix code. ④Each vertical cascade level is sorted according to the principles of ①, ②, and ③.

⑤ In the 16-line scanning display mode, a large LED screen is divided into 16 rows of the same name, and each row of the same name is arranged in dot matrix according to the principles of ①, ②, ③, and ④.

Take the data sorting of the first row of the same name row of a 128×64 dot matrix screen as an example, as shown in Figure 5, the storage order of the dot matrix code of the first row of the same name row should be: a, b...z, A, B,...z...



3 Conclusions

The use of parallel bus DMA data transmission technology simplifies the software and hardware design of the LED display system, reduces the system cost, and achieves good display quality. Under the system clock of 22.1184MHz, the display frame rate of 512×256 (8m2) monochrome dot matrix screen reaches 250Hz, and 1 byte is transmitted in an average of 120ns, achieving the purpose of using a single CPU system instead of a multi-machine system to control the LED display system. However, in order to make the previous generation of display driver boards still usable, the dot matrix codes need to be sorted, and can only be displayed in page mode, so a large-capacity memory is required for multi-page dynamic scrolling display. For a 512×256 monochrome dot matrix screen, tens of megabytes of capacity are required. The use of 32-bit ARM7TDMl core advanced controller S3C44BOX and cheap large-capacity SDRAM memory can solve this problem well. If a display driver board designed for DMA control display is used, the dot matrix code does not need to be sorted, and a SRAM of several hundred KB can meet the system requirements.