PWM variable frequency speed regulation system based on soft switching technology

1 Introduction

PWM (pulse width modulation) power conversion technology eliminates the need for bulky power frequency transformers, reduces the volume and weight of the device, and improves the power density and overall efficiency of the power supply . However, for PWM converters operating in a hard switching state, as the switching frequency increases, on the one hand, the switching loss of the switch tube will increase proportionally, reducing the efficiency of the circuit and the ability to handle power; on the other hand, it will generate serious electromagnetic interference (EMI). Since the power switch tube is not an ideal switch, it takes a certain amount of time to turn on and off. During this time, while the voltage (or current ) at both ends of the switch tube decreases, the current (or voltage) passing through increases, forming an overlap of the voltage and current waveforms, thereby generating switching losses. This article introduces a PWM variable frequency speed regulation system using soft switching technology, which greatly reduces switching losses. 2 Advantages of soft switching technology The so-called soft switching usually refers to zero voltage switching ZVS (zero voltage switching) and zero current switching ZCS (zero current switching z) or approximate zero voltage switching and zero current switching. The hard switching process is to complete the energy conversion process by interrupting the power flow through the sudden switching process; while the soft switching process is to make the current (or voltage) in the switching device change according to the sine or quasi-sine law through the resonance of the inductor L and the capacitor C. When the current naturally passes through zero, the device is turned off; when the voltage drops to zero, the device is turned on. The switching device completes the process of turning on and off under zero voltage or zero current conditions, so that the switching loss of the device is theoretically zero. The application of soft switching technology theoretically makes the switching loss of the switch tube zero, so that the switching frequency can be further increased, so that the power electronic converter has higher efficiency, higher power density, greatly reduced volume and weight, and higher reliability; and can effectively reduce the electromagnetic pollution (EMI) and environmental pollution (noise, etc.) caused by the power conversion device. 3 Topological structure and working principle of the ADRPI conversion bridge arm The auxiliary diode conversion pole inverter (ADRPI) topology is shown in Figure 1. If the circuit is defined as Q1 on and Q2 off as the "1" state, and Q2 on and Q1 off as the "0" state, then the basic working principle of this bridge arm conversion is:
















(1) Assume that the initial state of the circuit is the "1" state, that is, Q1 is turned on and Q2 is turned off. The pole voltage VC2 is clamped at the power supply voltage Vin due to the action of the clamping diode Dc. The inductor current iL is a stable positive value, and the inductor voltage VL is equal to zero. At this time, the inductor L exists as an energy storage element. The duration of this state is determined by the PWM modulation strategy of the system.

(2) When the circuit needs to change from the "1" state to the "0" state, Q1 is turned off under the action of the buffer capacitor CC1, and the inductor current iL continues to flow through the diode D2, and the inductor L resonates with the capacitor C2. When iL changes from a positive value to a negative value, Q2 naturally turns on under zero voltage conditions. When VC2 resonates to zero, the diode Dfw turns on, VC2 is clamped at zero value, iL remains at a stable negative value, VL is zero, and the circuit remains in the "0" state.

(3) When PWM modulation requires the circuit to change from the "0" state back to the "1" state, Q2 is turned off under the action of buffer capacitor CC2, iL continues to flow through diode D1, and L resonates with capacitor C1. When iL changes from a negative value to a positive value, Q1 is naturally turned on under zero voltage conditions. When VC2 resonates to Vin, diode Dc is turned on, VC2 is clamped to the power supply voltage Vin, iL remains at a stable positive value, VL is zero, and the circuit returns to the "1" state.

From the above ADRPI conversion bridge arm working process, it can be seen that the switching sequence Q1-D2-Q2-D1 provides the most superior switching environment for all switching devices. During the conduction process of Q1 and Q2, the voltage across the two ends of the switching device is detected by the base drive circuit with zero voltage detection to ensure that when diode D1 or D2 stops conducting, Q1 or Q2 is quickly turned on naturally, thus basically eliminating the conduction loss of the device. Moreover, fast diodes are not required in this process. Diodes D1 and D2 are naturally turned off after the current passing through them is zero. The turn-off process of Q1 and Q2 is completed under the action of buffer capacitors CC1 and CC2. At the moment when Q1 and Q2 are turned off, the voltage on them is zero, and then the dv/dt on them will be limited by CC1 and CC2, which completely eliminates the possibility of large current and high voltage existing at the same time during the turn-off process, thereby greatly reducing the turn-off loss. Diodes Dfw and Dc also have a very good working environment. The dv/dt on them is limited by the resonant capacitor, and the di/dt at turn-off is limited by the inductor L.

The high-power switch tube working in this zero-voltage switching mode can only be turned on when the voltage across its two ends is zero, which means that the other switch in the same bridge arm is under the full voltage at this time, that is, it has been turned off. Therefore, this technology fundamentally eliminates the possibility of power supply short circuit due to direct pass, making the operation of the inverter bridge arm highly reliable. The topology shown in Figure 1 is also called a rugged invert leg.

Using a rugged bridge leg, a stable DC power supply can be converted into an adjustable DC power supply. The output voltage changes from zero voltage to the power supply voltage as the duty cycle changes, and the power is allowed to flow in the opposite direction. This power supply can be used for two-quadrant DC drive control. Using two rugged bridge legs, a single-phase AC power supply can be formed. This inverter theoretically has no restrictions on the load power factor, so it can be used for uninterruptible power supply or single-phase AC drive control system.

We use three rugged bridge legs in the main circuit to form a three-phase AC inverter. This inverter can supply power to three-phase unbalanced loads with arbitrary power factors and can be used in three-phase AC drive control systems.

4 Design of control circuits and system application software

4 1 System control circuit

The system control circuit is shown in Figure 2.


The system control circuit uses 8051 single-chip microcomputer as the central unit, and 8253 16-bit programmable counter/timer, 8155 programmable RAM, I/O port expansion chip and EPROM to form the support circuit of HEF4752V. 8051 mainly completes the control work and sends time constants and control words to 8253. The three counters of 8253 generate fvct, ffct, frct and foct required by HEF4752V respectively. 8155 is used to expand I/O ports, accept control words, and give the switching frequency values ​​of each switching point. In view of the low accuracy requirements of this system, the control system adopts open-loop control. Using PWMIC makes the software and hardware design of the control system relatively simple. Moreover, this system has good protection and detection functions, and the harmonic number in the voltage waveform output by the system is also very high, which is very easy to filter out. HEF4752 is divided into 8 carrier segments, with carrier frequency ratios N=15, 21, 30, 42, 60, 84, 120, 168. The relationship between the carrier frequency ratio and the output frequency is shown in Table 1. Corresponding to each carrier frequency ratio segment, the FCT counter sends out 2N δi data for pulse width modulation. Under the same carrier frequency ratio N, the higher the fvct, the smaller the amplitude modulation ratio a, making the output voltage lower. In this way, a certain phase output signal with bilateral modulation is obtained. When the carrier frequency ratio N and fvct are determined, the change law of the modulation value δi in one cycle is also determined accordingly. Table 1 Relationship between carrier frequency ratio and output frequency










The frequency f of the SPWM wave output by HEF4752 is obtained by dividing the FCT clock counter by 3360. The switching frequency fr is obtained by dividing the FCT counter by 8 sets of frequency dividers corresponding to 8 values ​​of the carrier frequency ratio N. The frequency division numbers of these 8 sets of frequency dividers are 224 (corresponding to N=15), 160, 112, 80, 56, 40, 28, and 20 (corresponding to N=168). The maximum switching frequency frmax must be limited according to the switching frequency allowed by the switching device.

In order to avoid instability near the frequency ratio change point, a frequency ratio overlap area is set.

IGBT is voltage driven and has relatively high requirements for the drive circuit. Generally, there are drive circuits composed of discrete components and integrated dedicated drive circuits. This system uses the HL402 chip with dual short-circuit protection functions of first reducing the gate voltage and then soft shutting down. It has better performance, higher reliability of the whole machine and smaller size. 4 2 Design of system application software In the process of designing system application software, this system adopts the following measures: (1) Connection of each port of HEF4752 The three clock inputs of HEF4752 are output by the three counters of 8253. The output terminal "0" of the counter is connected to the FCT clock input terminal of HEF4752; the output terminal "1" of the counter is connected to the OCT and RCT clock input terminals of HEF4752V; the output terminal "3" of the counter is connected to the VCT clock input terminal of HEF4752. (2) Time constant of 8253 The counting clock of 8253 is 2MHz, and the time constants of the three channels are 0#ffct0012H 1#frct, foct0007H 2#fvct0008H In the program, we specify the control mode word as shown in Table 2. Table 2 Contents of control mode word
























8051 reads the control mode word and output frequency from 8155, sends the corresponding time constant to 8253, and controls according to the control mode provided by the control mode word. When the system does not receive an interrupt signal, it still outputs in the previous mode. When the system receives an interrupt signal, 8051 will re-read the control mode word and given frequency and change the output state.