Design of MOSFET drive circuit for electric bicycle controller

Electric bicycles are environmentally friendly, energy-saving, reasonably priced, noiseless, and convenient. Therefore, electric bicycles have become the main means of transportation for people in today's society. At the same time, consumers and businesses have higher and higher requirements for the quality and reliability of the whole vehicle. The reliability of the controller, as one of the four major parts of the whole vehicle, is particularly important. The design of power MOSFET and related drive circuits is directly related to the reliability of the controller, especially on the freewheeling side. If the drive circuit of MOSFET is not designed properly, the freewheeling side MOSFET is easily damaged. Therefore, this article studies how to measure, analyze and adjust the MOSFET drive circuit of the controller to improve the reliability of MOSFET, so as to provide some reference for designers when designing products.

1 MOSFET switching process and MOSFET parameter model

1.1 MOSFET Turn-On Process

The waveform of the MOSFET during the turn-on process is shown in Figure 1. The turn-on process can be divided into four stages:

Phase A, t0¬—t1: Gate voltage Vgs gradually rises from 0V to Vth. During this period, MOSFET is turned off, Vds remains unchanged, and Id=0A.

Phase B, t1-t2: The gate voltage Vgs rises from Vth to the platform voltage Vp, and the gate voltage charges Cgs. During this period, the MOSFET begins to conduct and enters the saturation state, Vds remains basically unchanged, and Id rises from 0 to Id (max).

Phase C, t2-t3: The gate voltage Vgs remains unchanged, and the gate voltage charges Cgd. During this period, the MOSFET is still in saturation, Vds drops rapidly, and Id remains unchanged.

Phase D, t3-t4: The gate voltage Vgs continues to rise from Vp, during which the MOSFET exits the saturation state and enters the fully on state.
The waveform when the MOSFET is turned off is opposite to that when it is turned on, so it will not be described here.

1.2 MOSFET parasitic parameters

The MOSFET parasitic parameter model is shown in Figure 2. Due to the influence of the MOSFET structure, leads and package , after the MOSFET is manufactured, there are PN junction parasitic capacitance and parasitic inductance between its pins, and lead inductance on the pins. Since the source lead is longer, Ls is generally larger than Ld.

Therefore, we should pay special attention to the influence of parasitic capacitance and lead inductance on the switching waveform in actual switching applications, especially when the load is inductive. The input capacitance, reverse transfer capacitance and output capacitance of MOSFET are expressed as follows:

Ciss=Cgs+Cgd

Crss=Cgd

Coss=Cgd+Cds

2 Two common MOSFET drive circuits

2.1 Driving circuit composed of discrete devices

The driving circuit composed of discrete devices (as shown in Figure 3) has the following working principle:

A. When HS is high, Q7 and Q4 are turned on, Q6 is turned off, and the voltage on capacitor C4 (about 14V) is added to the gate of Q5 through Q4, D3, and R6, turning Q5 on. During the on-time, the source voltage (Phase) of Q5 is close to the power supply voltage Vdc, so the voltage across the capacitor floats with the Phase voltage. Capacitor C4 is also called a bootstrap capacitor. Q5 relies on the voltage across C4 to maintain conduction.

B. When HS is low, Q7 and Q4 are turned off, Q6 is turned on, and a discharge circuit is provided for the gate of Q5, so that Q5 is turned off quickly. After Q5 is turned off, the Phase voltage drops close to 0V due to the opening of the lower tube or the effect of the load, so that C4 is charged through the +15V→D2→C4→GND circuit, ready for the next turn-on.

C. When LS is at a low level, Q8 and Q11 are turned on, Q10 is turned off, and the drive circuit charges the gate of the lower tube Q9 through R11, turning Q9 on.

D. When LS is at a high level, Q8 and Q11 are turned off, Q10 is turned on, providing a discharge circuit for the gate of Q9, causing Q9 to be turned off.

E. When HS and LS are both high, the upper tube is turned on and the lower tube is turned off. When HS and LS are both low, the upper tube is turned off and the lower tube is turned on. In practical applications, in order to avoid the upper and lower tubes being turned on at the same time, the logic of HS and LS must be guaranteed by the MCU or logic circuit.

2.2 Half-bridge Driver Chip Driver Circuit

The driving circuit composed of the half-bridge driving chip is shown in Figure 4, and the working principle is as follows:

A. When HS and LS are both high, HO has a drive voltage output, turning on Q1. When HS and LS are both low, LO has a drive voltage output, turning on Q2.

B. Capacitor C2 has the same function as C4 in the discrete device driver circuit and is also a bootstrap capacitor.

C. Capacitor C1 is a decoupling capacitor. This capacitor should generally be added to suppress the interference to the floating power supply of the driving circuit when the power MOSFET is switched.

2.3 The difference between the two drive circuits

A. Both drive circuits can provide basically the same drive current to drive MOSFET to turn on when turned on , but when MOSFET is turned off, the discrete device drive circuit can provide a larger discharge current to turn off MOSFET because of the transistor discharge, while the half-bridge drive circuit has to discharge through the gate resistor , so the discharge current is relatively small, resulting in a long MOSFET off time and a corresponding increase in switching loss. The solution can be to connect a diode in reverse parallel to the drive resistor and add a discharge PNP transistor. B. The discrete device drive circuit uses more devices and is less reliable than the drive circuit of the half-bridge chip. But the prerequisite is that the drive circuit of the half-bridge drive chip must be reasonably designed.

3 MOSFET drive circuit requirements and parameter adjustment

The gate voltage cannot exceed the maximum value of Vgs. When designing the drive circuit, the anti-interference performance of the drive power supply voltage and the circuit should be considered to ensure that the gate voltage of the MOSFET does not exceed the maximum value of Vgs when it is in a switching state with an inductive load.

In order to reduce the switching loss of MOSFET, the drive circuit should be able to provide a sufficiently large drive current to make the turn-on and turn-off time as short as possible, and at the same time, minimize the high-frequency oscillation of the gate voltage. If the same RC time constant is to be obtained, using a smaller drive resistor and a larger capacitor can obtain better drive characteristics, but the loss of the drive circuit will also increase.

Figures 5 and 6 are test waveforms in actual applications. From the figures, we can see that: ① The increase in capacitance makes the turn-on time longer and increases the turn-on loss. ② The increase in capacitance reduces the high-frequency oscillation of the gate voltage. At the same time, due to the reduction in the oscillation of the Miller platform, the loss of the MOSFET during the Miller platform will also be reduced accordingly.

Prolonging the on-time of the MOSFET can reduce the inrush current when it is turned on. Since the motor load is an inductive load, there is a freewheeling phenomenon when the PWM is turned off (see I2 in Figure 7). In order to reduce the size of the reverse recovery current (Irr) on the freewheeling side, the on-speed of the PWM side switch tube should not be too fast. Since there is a formula when the MOSFET is in the saturation region: Id=K*(Vgs-Vth)2, (K is a constant determined by the characteristics of the MOSFET). Therefore, under certain temperature and Vds conditions, the current size in the MOSFET can be determined from the gate drive voltage Vgs of the MOSFET. The Vgs peak value in Figure 5 is 9.1V, and the Vgs peak value in Figure 6 is 6.4V, so increasing the capacitance reduces the peak current. Id can also be obtained from the transfer characteristic diagram of the MOSFET.

Due to the presence of MOSFET package inductance and line stray inductance, when the MOSFET reverse recovery current Irr is suddenly turned off, the voltage Vds on the MOSFET (Q3) will ring (as shown in CH2 in Figure 8). The appearance of this ringing will cause Vds to exceed the breakdown voltage of the MOSFET and cause an avalanche phenomenon. If ringing occurs in the line, we can reduce the ringing by the following methods:

A. When designing the circuit, the following considerations should be taken into account: ① Try to shorten the trace length between the drive circuit and the MOSFET; ② Make the copper foil routing of the large current loop as short and wide as possible, and add tin to the copper foil surface when necessary; ③ Reasonable routing to minimize the area of ​​the large current loop.

B. If the line stray inductance has been determined, the Vds ringing on the MOSFET on the freewheeling side can be reduced by reducing the MOSFET turn-on speed on the PWM side, so that the Vds on the MOSFET does not exceed the maximum withstand voltage value.

C. If the above two methods cannot solve the problem well, we can suppress the line ringing by adding a snubber on the phase line.

Note the gate induced voltage generated by Cdv/dt . As shown in Figure 7: During the on-switching of control MOSFET Q1, the full input voltage is not immediately present at the drain of Q3 because of the Miller effect and turn-on delay of Q1. The drain voltage applied to Q3 induces a current coupled through its gate-drain Miller capacitance Cgd (see Figure 2) . This induced current produces a voltage drop across Q3's internal gate resistor Rg and external gate resistor. This voltage charges the gate-source capacitance Cgs on Q3's gate. The magnitude of the induced gate voltage on Q3 is a function of dv/dt, Cgd, Cgs, and the total gate resistance.

The induced gate voltage is shown in CH1 in Figure 8, and its value has reached 2.3V. In addition, due to the existence of the source lead inductance, when the current in Q3 decreases rapidly, a voltage with a negative polarity at the top and a positive polarity at the bottom will be induced at both ends of Ls, as shown in Figure 9. At this time, the voltage Vgs (die) applied to DIE is greater than the Vgs voltage measured on the external pin, so due to the influence of Ls, the MOSFET may be turned on in advance. If the lower tube is turned on due to the induced voltage, it will cause the upper and lower tubes to punch through. If the MOSFET cannot withstand this punch-through current, the MOSFET will be damaged.

Methods to prevent Cdv/dt inductive conduction:

A. Choose a MOSFET with a higher threshold voltage.

B. Choose a MOSFET with smaller Miller capacitance Cgd and smaller Cgd/Cgs.

C. Slow down the opening speed of the upper bridge (Q1), thereby reducing the dv/dt and di/dt during shutdown, and reducing the induced voltage Cdv/dt and Lsdi/dt.

D. Increase the gate capacitance Cgs of Q3 to reduce the induced voltage.

Preserve the benefits of Cdv/dt sensing turn-on

Cdv/dt inductive conduction has a benefit: it can reduce the voltage spike and Vds ringing on the freewheeling side MOSFET (V = L×dIrr/dt; L: loop parasitic inductance), and also reduce the EMI interference of the system. Therefore, when designing the MOSFET drive circuit, we should weigh the adjustment of the drive parameters according to the actual situation, that is, whether to prevent Cdv/dt inductive conduction to maximize the circuit efficiency and reliability or to use Cdv/dt inductive conduction to suppress excessive parasitic ringing.

4 Conclusion

4.1 Before starting the design, you should fully understand the parameters of the selected MOSFET to determine whether the MOSFET can meet the product requirements, including the MOSFET's withstand voltage (Vgs and Vds), maximum current and other parameters, to ensure that these parameters do not exceed the maximum rated value of the MOSFET when the working conditions are the worst.

4.2 During the circuit design stage, thermal design must be performed to ensure that the MOSFET operates in a safe operating area. Special attention should be paid to the wiring of the circuit board to minimize the stray inductance of the circuit.

4.3 Try to shorten the switching time and minimize the switching loss without affecting the reliability. Sometimes, synchronous rectification can be used to further improve efficiency and reduce temperature rise.