A brief discussion on the principles of power supply and grounding design for WiFi transceivers

1 Basic principles of power routing and power bypassing

When designing RF circuits, the design of the power circuit and the layout of the circuit board are often left until the design of the high-frequency signal path is completed. For designs that are not well thought out, the power supply voltage around the circuit can easily produce erroneous outputs and noise, which will have a negative impact on the system performance of the RF circuit. Reasonable allocation of PCB board layers, VCC pins using star topology, and appropriate decoupling capacitors on the VCC pins will help improve the performance of the system and obtain the best indicators. Reasonable PCB layer allocation is convenient for simplifying subsequent wiring processing. For a four-layer PCB (a circuit board commonly used in WLAN), in most applications, the top layer of the circuit board is used to place components and RF pins, the second layer is used as the system ground, the power supply part is placed on the third layer, and any signal lines can be distributed on the fourth layer. The use of an undisturbed ground plane layout on the second layer is very necessary for establishing an impedance-controlled RF signal path, and it is also convenient to obtain the shortest possible ground loop, provide a high degree of electrical isolation for the first and third layers, and minimize coupling between the two layers. Of course, other board layer definitions can also be used (especially when the circuit board has different numbers of layers), but the above structure is a proven successful example. A large power plane can make VCC wiring easy, but this structure is often the fuse that causes system performance to deteriorate. Connecting all power leads together on a large plane will not avoid noise transmission between pins. On the contrary, if a star topology is used, the coupling between different power pins will be reduced. Figure 1 shows a star-connected VCC wiring scheme, which is taken from the evaluation board of the MAX2826IEEE802.11a/g transceiver. In the figure, a main VCC node is established, and power lines of different branches are drawn from this point to power the power pins of the RFIC. Each power pin uses an independent lead, which provides spatial isolation between the pins and helps to reduce the coupling between them. In addition, each lead also has a certain parasitic inductance, which is exactly what we want, and it helps to filter out high-frequency noise on the power line.

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It is best to place a large capacitor, such as 2.2μF, at the main node of the VCC star topology. This capacitor has a low SRF and is very effective in eliminating low-frequency noise and establishing a stable DC voltage. Each power pin of the IC requires a low-capacity capacitor (such as 10nF) to filter out high-frequency noise that may be coupled to the power line. For those power pins that power noise-sensitive circuits (for example, the power supply of the VCO), two bypass capacitors may be required. For example: using a 10pF capacitor in parallel with a 10nF capacitor to provide bypass can provide decoupling over a wider frequency range and minimize the impact of noise on the power supply voltage. Each power pin needs to be carefully examined to determine how large the decoupling capacitor is required and at which frequency points the actual circuit is susceptible to noise interference. Good power supply decoupling technology combined with rigorous PCB layout and VCC leads (star topology) can lay a solid foundation for any RF system design. Although there will be other factors that reduce system performance indicators in actual designs, having a "noise-free" power supply is a basic element for optimizing system performance.

2 Basic principles of RF grounding and via design

The layout of the ground layer and the leads are also key to the design of WLAN circuit boards. They will directly affect the parasitic parameters of the circuit board and have the potential to reduce system performance. There is no unique grounding solution in RF circuit design. Several ways can be used to achieve satisfactory performance indicators in the design. The ground plane or lead can be divided into analog signal ground and digital signal ground, and circuits with large current or power consumption can be isolated. According to the design experience of previous WLAN evaluation boards, using a separate ground layer in a four-layer board can achieve better results. With this experience, using the ground layer to isolate the RF part from other circuits can avoid cross-interference between signals. As mentioned above, the second layer of the circuit board is usually used as the ground plane, and the first layer is used to place components and RF leads.

After the ground layer is determined, all signal grounds are connected to the ground layer with the shortest path. Usually, vias are used to connect the ground wire on the top layer to the ground layer. It should be noted that vias are inductive. The physical model of the via is shown in Figure 4. Figure 5 shows the precise electrical characteristic model of the via, where Lvia is the via inductance and Cvia is the parasitic capacitance of the via PCB pad. If the ground layout techniques discussed here are used, parasitic capacitance can be ignored. A 1.6mm deep via with a diameter of 0.2mm has an inductance of approximately 0.75nH, and an equivalent reactance of approximately 12Ω/24Ω in the 2.5GHz/5.0GHz WLAN band. Therefore, a ground via cannot provide a true ground for the RF signal. For high-quality circuit board design, as many ground vias as possible should be provided in the RF circuit section, especially for the exposed ground pads in general IC packages. Poor grounding can also cause radiation in the receiving front end or power amplifier section, reducing the gain and noise figure indicators. It should also be noted that poor welding of the ground pad will cause the same problem. In addition, the power consumption of the power amplifier also requires multiple vias connected to the ground layer.

The benefits of VCC decoupling include filtering out noise from other circuits, suppressing locally generated noise, and eliminating cross-interference between stages through power lines. If the decoupling capacitors use the same ground via, due to the inductance effect between the via and the ground, the vias at these connection points will carry all RF interference from the two power supplies, not only losing the function of the decoupling capacitors, but also providing another path for inter-stage noise coupling in the system. As will be seen in the discussion in the third part of this article, the implementation of PLL always faces great challenges in system design, and a good ground layout is necessary to obtain satisfactory spurious characteristics.

3 Suppress PLL spurious signals through proper power bypassing and grounding Meeting

the requirements of the 802.11a/b/g system transmit spectrum mask is a difficult point in the design process. Linearity indicators and power consumption must be balanced, and a certain margin must be left to ensure compliance with IEEE and FCC regulations while maintaining sufficient transmit power. The typical output power required by the IEEE802.11g system at the antenna end is +15dBm, and -28dBr at a frequency deviation of 20MHz. The power rejection ratio (ACPR) of adjacent channels in the frequency band is a function of the linear characteristics of the device, which is correct for specific applications under certain conditions. A lot of work on optimizing the ACPR characteristics in the transmit channel is achieved by adjusting the bias of the TxIC and PA based on experience, and tuning the matching networks of the input, output and intermediate stages of the PA.

The above discussion raises another question, which is how to effectively limit the PLL spurious components to a certain range so that they do not affect the transmit spectrum. Once the spurious components are found, the first solution that comes to mind is to narrow the bandwidth of the PLL loop filter to attenuate the amplitude of the spurious signal. This method is effective in rare cases, but it has some potential problems. Figure 8 shows a hypothetical situation. Assuming that a 20MHz relative frequency N-fractional synthesizer is used in the design, if the loop filter is second-order, the cutoff frequency is 200kHz, and the roll-off rate is usually 40dB/decade, 80dB of attenuation can be obtained at 20MHz. If the reference spurious component is -40dBc (assuming that the level can cause harmful modulation components), the mechanism that generates spurious may be beyond the range of the loop filter (if it is generated before the filter, its amplitude may be very large). Compressing the bandwidth of the loop filter will not improve the spurious characteristics, but will increase the PLL lock time, which has a significant negative impact on the system.

Experience has shown that the effective way to suppress PLL spurious is reasonable grounding, power layout and decoupling technology. The wiring principles discussed in this article are a good design start to reduce PLL spurious components. Considering the large current changes in the charge pump, it is necessary to use a star topology. If there is not enough isolation, the noise generated by the current pulse will be coupled to the VCO power supply and modulate the VCO frequency, which is usually called "VCO pulling". Isolation can be improved by physical spacing between power lines and decoupling capacitors for each VCC pin, properly placing ground vias, and introducing a series ferrite component (as a last resort). The above measures do not need to be used in every design. Appropriate use of each method will effectively reduce the spurious amplitude. Figure 9 provides a result of an unreasonable VCO power supply decoupling scheme. The power supply ripple shows that it is the switching effect of the charge pump that causes strong interference on the power supply line. Fortunately, this strong interference can be effectively suppressed by adding bypass capacitors. Figure 10 shows the measurement results at the same point after the circuit is changed.

In addition, if the power supply wiring is unreasonable, for example, the power supply lead of the VCO is located just below the charge pump power supply, the same noise can be observed on the VCO power supply, and the generated stray signal is enough to affect the ACPR characteristics. Even if the decoupling is strengthened, the test results will not be improved. In this case, it is necessary to examine the PCB wiring and rearrange the power supply lead of the VCO, which will effectively improve the stray characteristics and meet the indicators required by the specification.