Design of embedded wireless video monitoring system based on DSP chip TMS320DM642

TMS320DM642 is selected as the system CPU, and the latest video coding standard H.264 compression algorithm is adopted to realize the wireless video monitoring and video data storage system based on CDMA network transmission.

With the launch of GRPS and CDMA1x public wireless data networks by operators in most parts of China, video transmission through public wireless data networks has become a hot topic in research and application, which can completely solve the short-distance problem of microwave methods. Since the bandwidth of public wireless data networks is relatively narrow and unstable, the use of video compression algorithms with low coding efficiency (such as H.263, MPEG-4, etc.) has unsatisfactory transmission effects and cannot meet the requirements of most monitoring occasions.

H.264 is the latest video compression standard developed by JVT. It has a bit rate 50% lower than H.263 and MPEG-4 at the same quality. It also supports wireless network transmission. However, its computational complexity is 3-5 times that of H.263 and MPEG-4, so general CPU systems cannot meet the requirements. TMS320DM642 is TI's latest high-performance digital media processor, with instructions up to 4800 MIPS, which can meet the requirements of real-time H.264 encoding algorithms.

This paper designs an embedded system based on TMS320DM642, uses H.264 video encoding algorithm, and successfully develops a wireless video surveillance system based on CDMA transmission.

1 Composition of wireless video surveillance system

1.1 Wireless Video Surveillance System Design Requirements

This system requires the use of an embedded video sending terminal to compress the collected video images in real time and send them through the CDMA network. The receiving end uses a PC to decode and display the received video data. The requirements for the embedded video sending terminal are as follows:

①One PAL/NTSC standard analog video input, one analog audio input;

②Use CDMA access to send video data through the network;

③Use CF card or hard disk to store the video locally;

④ The size and frame rate of sending and saving images are adjustable;

⑤Can be remotely controlled via wireless network and requires low power consumption.

1.2 Overall design of the system

Since the bandwidth of CDMA wireless network is narrow and the bandwidth fluctuation is large, H.264 is used as the video compression algorithm in the system. At the same time, the local storage and CDMA transmission video are different in image size and frame rate, so two encoding structures are needed to encode them respectively.

Figure 1 shows the overall structure of the system. The system mainly includes DM642CPU, video input, audio input/output, hard disk interface, serial port and USB communication (USB2.0) and other main functional modules. In addition, it also includes real-time clock (RTC), display and I/O interface (LCD&I/O), SDRAM, FLASH and power supply (POWER) modules. The following will analyze and design each functional module in detail.

Figure 1 Video transmission terminal system block diagram

2 Hardware Design of Wireless Video Surveillance System

2.1 Introduction to TMS320DM642

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TMS320DM642 is a high-performance digital media processor launched by TI for multimedia processing applications. This processor is specially tailored for the video and imaging market, especially suitable for VOIP video, video on demand (VOD), multi-channel digital video recording applications and high-quality video encoding and decoding solutions.

The DM642 processor integrates the TMS320C64X DSP core. At a running speed of 600MHz, the instruction speed can reach 4800MIPS. Due to its powerful computing ability, it can implement real-time H.264 encoding and decoding algorithms.

DM642 integrates an external memory interface (EMIF) control unit, which can be directly connected to external SDRAM and FLASH through 20 address lines and 64-bit data bus. In this system, since 100MHz SDRAM is used, considering the signal integrity, SDRAM is directly connected to DM642, and FLASH is connected after being driven through the bus.

2.2 Video Input Module

DM642 has three video ports, supporting multiple resolutions and standards, such as CCIR601, ITU-BT.656, BT.1120, etc. Each port is 20 bits wide and can be flexibly configured as a 20/16 bit or two 10/8 bit channels. At the same time, each port can be configured as video input or video output. In this system, VP0 is connected to SAA7113H for video input acquisition.

SAA7113H is a 9-bit video decoder, which consists of a two-channel analog pre-processing circuit consisting of video source selection, anti-aliasing filter and ADC, gain control, clock generation circuit (CGC), multi-standard digital decoder, brightness saturation control circuit, etc.

It supports multiple video input formats such as PAL and NATSC, and outputs the standard ITU.656YUV 4∶2∶28bit format. It is controlled via the I2C bus and only requires a 24.576MHz external crystal oscillator. It uses a 3.3V power supply and has a power consumption of less than 0.5W. The interface between SAA7113H and DM642 is shown in Figure 2.

Figure 2 SAA7113H and DM642 interface

2.3 Audio Input and Output (CODEC) Module

DM642 has a multi-channel audio serial port (McASP) and two multi-channel buffered serial ports (McBSPs), but they are multiplexed with the video port. In this system, McBSPs1 in VP1 is used as the interface to connect to the audio Codec.

TLV320AIC23B is a high-performance stereo audio Codec chip launched by TI. It has a built-in headphone output amplifier, supports two input modes (MIC and LINEIN) (choose one of the two), and has programmable gain adjustment for both input and output.

The analog-to-digital conversion (ADCs) and digital-to-analog conversion (DACs) components of AIC23B are highly integrated inside the chip, and adopt advanced Sigma-delta oversampling technology. They can provide 16-bit, 20-bit, 24-bit and 32-bit sampling in the frequency range of 8k to 96k. The output signal-to-noise ratio of ADC and DAC can reach 90dB and 100dB respectively.

AIC23B also has very low power consumption, with power consumption of only 23mW in playback mode.

The interface between AIC23B and DM642 is shown in Figure 3.

Figure 3 AIC23B and DM642 interface

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2.4 CDMA wireless transmission serial port module

This system uses the Q2358C serial interface module as the CDMA access device, which supports voice communication, Chinese and English text messages, dual-tone multi-frequency (DTMF) and other functions. The baud rate ranges from 300 to 115,200 bit/s, supports a maximum Internet speed of 153 kb/s, and uses the AT instruction set to communicate through the RS-232 serial port. DM642 does not have an asynchronous universal serial interface, and an extended asynchronous communication chip is required to achieve serial communication.

TL16C752B is a UART transceiver with a maximum baud rate of 3Mb/s (when using a 48MHz clock source). It has a 64-byte send/receive FIFO inside. The start and stop of the receive FIFO can be realized through software programming. It supports multiple baud rates and multiple serial data formats. The DM642 is connected to it using EMIF control. The address lines A0~A2, data lines D0~D7, and read/write control signals IOR/IOW are connected to the driven bus, and the selection signals CSA/CSB are generated by GAL. The TL16C752B and Q2358C modules are connected through a level conversion connection via MAX3243. Figure 4 shows a serial interface connection method.

Figure 4 System serial communication interface

2.5 DE and USB communication module

In this system, the collected video needs to be stored locally, using CF card or IDE hard disk to save the data, and the data stored in the CF card or IDE hard disk can be read out when needed through USB2.0. The DM642 and IDE interface are controlled by the signal generated by GAL16LV8.

TUSB6250 uses a USB2.0 to ATA/ATAPI bridge with an embedded 8051 core, which is fully compatible with the USB2.0 standard and supports eight configurable terminals (four inputs and four outputs). It integrates the USB storage device transmission protocol internally and connects seamlessly with ATA/ATAPI devices.

The internal integrated 60MHz8051 microprocessor has an instruction speed of up to 30MIPS, and the 40kbyte RAM can be flexibly configured as data or code RAM. The 13 general I/O ports can be used for various communications and control purposes, and there is an I2C interface. In this system, the communication between DSP and TUSB6250 is realized through I2C and HPI bus. The DE and USB interface are shown in Figure 5.

Figure 5 DM642 and IDE and USB interfaces

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2.6 Power supply and other modules

DM642 uses dual power supply, the core power supply is 1.4V and the current consumption is 890mA; the I/O power supply is 3.3V and the current consumption is 210mA. Since the core power supply voltage is low and the current consumption is large, if the LDO power supply efficiency is low, the power consumption will increase. Therefore, two switching power supply chips TPS54310 are used in this system to generate 3.3V and 1.4V power supplies respectively, and the power efficiency can reach more than 90%.

DM642 provides 16 general I/Os, through which keyboard input, control switch input and output are realized. DM642's video port VP3 is configured as output and directly connected to LCD. In addition, the system uses DS1338 as a real-time clock to provide real-time time information.

3 Considerations in system design

3.1 Schematic Design

The internal operating frequency of DM642 is obtained by multiplying the external clock input by the internal PLL. The PLL multiplication can be selected by the CLKMODE1 and CLKMODE2 pins to be x1, x6 or x12. Therefore, these two pins must be connected to corresponding resistors to be adjustable so that DM642 can run at different speeds.

DM642 has multiple BOOT modes to choose from. If you choose EMIFA FLASH as the boot mode, the chip select of FLASH must be connected to TCE1. The selection of the big/small mode of the optional byte order of DM642 and the PCI, HPI, and EMAC modes of the peripherals are determined by the levels of the LENDIAN, PCI_EN, PCI_EEAI, HD5, and MAC_EN pins during reset. It is important to consider making the level values ​​adjustable during reset.

For the emulator, ensure that EMU[1∶0] is pulled up and TRST is pulled down. In addition, ensure that the AARDY pin is high when not in use, and the NMI pin is grounded when not in use. When selecting the HPI mode, ensure that the HPI control signal level is correct, and handle other unused input pins correctly.

3.2 PCB Design

As a high-performance digital media processor, DM642 not only has a very high internal operating frequency of 600MHz, 720MHz and 1GHz, but also has a bus speed of 100MHz or 133MHz with the external SDRAM. If the external SDRAM cannot reach the desired speed due to wiring reasons, the system performance will be reduced.

For signal buses above 100MHz, there are signal integrity issues. To ensure signal integrity, the following methods are used: the clock line of SDRAM should be as short as possible, and the length to two SDRAMs should be as equal as possible; other peripherals such as FLASH should not be directly connected to the data and address buses, but should be connected through buffer chips (such as SN74LVT16245B); a small resistance should be connected in series on the high-speed bus, and the resistance value can be obtained through simulation, and the line is required to be more impedance-limited.

DM642 has PLL inside. The devices connected to the PLL outside should be as close to the chip as possible and must be placed on one side of the circuit board. The length of the JTAG connection cannot exceed 6in. If it exceeds 6in, a driver must be added. This system has both analog and digital parts. Pay attention to the design of analog power supply and digital power supply, and try to reduce the interference of digital signals on analog signals. Otherwise, there will be snow and stripes on the collected video signal, and noise on the audio signal. Use separate power supply chips to power the video and audio chips as much as possible, and the analog ground and digital ground should be connected at a single point or with magnetic beads.

4 Conclusion

According to the above hardware design, an embedded wireless video surveillance system based on DM642 is completed. The system takes high-speed DSP as the core and is supplemented by corresponding peripheral circuits to realize real-time H.264 video encoding and decoding. At present, the system has been successfully debugged and runs stably, providing a practical solution for wireless video surveillance in public security, transportation, water conservancy and other industries, with very high application value.