Design of a portable automatic test system for new radar digital circuits

Abstract: With the maintenance and support of digital circuits of new radar equipment as the background, a method for establishing the "MERGE" boundary scan test model is proposed. Based on this method, a complete portable digital circuit automatic test system is designed to solve the defects of high development cost, high technical difficulty and low fault coverage of ICT test, functional test and traditional boundary scan test TPS. The test system has now successfully undertaken the maintenance and support tasks of digital circuits of new radar equipment. The application shows that the system has the advantages of reasonable design, stable and reliable performance, and accurate fault isolation.

introduction

Radar, as an important military weapon, is likened to the "eyes" of combat commanders in the military, and plays a vital role in maintaining national security and territorial integrity. However, with the development of digital circuit design and manufacturing technology, especially the advancement and improvement of CAD design software, single testing methods such as ICT (In-Circuit Test) testing and functional testing can no longer meet the requirements of new radar digital circuit testing and fault diagnosis. Boundary scan [1] testing will become the mainstream technology for the development of digital circuit fault diagnosis of radar equipment in the future.

Based on the in-depth discussion of the limitations of ICT testing and functional testing, as well as the research and practice of boundary scan testing technology, this paper proposes a method for establishing a "MERGE (combination)" boundary scan test model, and based on this method, a portable digital circuit
automatic test system is constructed to achieve high-speed and accurate testing of new radar digital circuits. The system has
the advantages of compact and portable hardware equipment, stable and reliable performance, and high fault isolation rate. It is suitable for battlefield-level real-time maintenance and support, and is an effective supplement to large-scale online testing and functional
testing platforms. It has better solved the problems of test equipment being controlled by people and emergency repairs during wartime.

Automatic test system implementation

Establishment of the “MERGE” test model

The IEEE 1149.1 standard clearly defines the boundary scan construction principle and the corresponding test method. In the fault diagnosis process,
the boundary scan structure and related test instructions of the VLSI chip can be used to effectively detect the
fault types such as fixed pin, open circuit, and bridge of the VLSI chip [2]. However, the digital circuit module to be tested usually includes boundary scan devices and non-boundary scan devices.
The MERGE test model proposed in this paper can test non-boundary scan chips through the existing boundary scan structure, which can expand
the test scope of boundary scan and improve the fault coverage of TPS.

Based on the basic principles of boundary scan test technology, a "MERGE" structural test model was creatively proposed in the process of building a test system
. The basic idea is shown in Figure 1.

Among them, part B is the digital circuit BUT to be tested, and part A is a boundary scan expansion card independent of BUT. This expansion card can be
regarded as a digital circuit that complies with the IEEE 1149.1 boundary scan design specification. First, a complete digital circuit
BUT is divided into the following parts: non-boundary scan chip cluster (U1), boundary scan chip cluster (U2), and mixed chip cluster (U3). The concept of "cluster" here refers to multiple devices collectively as a "cluster". The range of the cluster can be divided according to the specific circuit scale, which can be as small as a single IC or UUT (Unit Under Test) or as large as a complete BUT (Board Under Test).

(1) MERGE non-boundary scan chip cluster (U1): Non-boundary scan chips are an ordered subset of the entire BUT network and
are circuits with specific functions. In the MERGE concept, a separate functional model is established for the non-boundary scan chip cluster, which is used
as an intermediate signal transmission model between boundary scan chips, MERGE to the boundary scan link, and combined with the EXTEST boundary scan instruction, through Capture IR-->Shift IR-->Update IR-->Capture DR-->shift DR-->Update
DR and other corresponding operations, the purpose of testing the non-boundary scan cluster through the boundary scan link is achieved.

(2) MERGE hybrid chip cluster (U3): A hybrid chip cluster refers to a hybrid circuit that contains both non-boundary scan chips and boundary scan chips
(it may also contain some intermediate analog circuits). The idea of ​​MERGE is similar to (1). The model verification can be achieved
by applying a set of certain test vectors to MI (Model Input), and after a certain time delay,
comparing the sampled response signal with the expected value stored in the register at MO (Model Output)
.

(3) MERGE BSEC (Boundary Scan External Card), through BSEC,
the boundary scan test is performed on the non-boundary scan chip cluster in the BUT edge circuit or the BUT without boundary scan chip. During the test, the BUT to be tested is regarded as
a non-boundary scan cluster or a mixed boundary scan cluster, and the BSEC is regarded as a boundary scan chip cluster. Through the MERGE method, the BUT,
interface circuit, and boundary scan expansion card circuit are virtualized into a BUT with boundary scan chip. The specific implementation
is similar to (1) and (2).

Test system hardware design

In order to reduce the weight of the whole system and facilitate transportation and carrying, the front-end equipment of this test system uses a laptop computer as the main
body to complete the realization of system functions and the interaction of the human-machine interface [3]. At the same time, it is equipped with a GPIB-USB module and
a JTAG-Control-PCI-USB controller to control the programmable power supply (Agilent 6600) and the BS Interface Pod
module respectively. The core of the entire hardware design is the BSEC (boundary scan expansion card), JTAG-Control-PCI-USB controller and BS
Interface Pod module. The system hardware block diagram is shown in Figure 2.

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BSEC (Boundary Scan Expansion Card)

The MERGE boundary scan expansion card adopts a testability design that complies with the IEEE 1149.1 boundary scan standard. It uses 5
XILINX XC95144 chips to build a complete boundary scan link from TDI to TDO. The upstream
and downstream circuits of the scan link use 74ACQ244 to buffer and shape the signal to enhance the fan-out capability of the upstream circuit. At the same time, the edge
connector of the entire board uses a solid, reliable, and corrosion-resistant European Eurocard structure connector to ensure that the test signal
is stable and reliable. The schematic diagram is shown in Figure 3.

JTAG-Control-PCI-USB Controller

The JTAG-Control-PCI-USB controller is the main component for signal control between the test system laptop computer and the unit under test (BUT)
, realizing the conversion of parallel control instructions and data of the industrial computer to serial instructions and data that conform to the boundary scan test protocol
. The circuit adopts the circuit design mode of DSP+CPLD. The DSP chip adopts TI's TMS320LF2407A, which
can run at a speed of up to 40MIPS (25ns), with at least 544 words of on-chip dual-access memory DARAM, 2K
on-chip single-access memory SARAM, and 32K on-chip program memory FLASH; the CPLD uses ALTERA's
MAX7000S series EPM71285, which has an integration level of 600~5000 available gates, 32~256 macro units and
36~155 user-defined I/O pins, and its 3.3V I/O level is compatible with the DSP chip port level, and can be
programmed and debugged online through the I/O pin JTAG interface that conforms to the industrial standard. The JTAG-Control-PCI-USB controller is
a PCI/IEEE 1149.1 standard master control unit. When used in conjunction with the BS Interface Pod, it controls the IEEE 1149.1
standard adaptive test bus and the discrete signals that adapt to it. At the same time, the controller can also control the low voltage differential signal (based on TIA /EIA-644 and IEEE 1596.3 standards) applied to the test bus
for the JTAG-Control-PCI-USB controller to communicate with the BS Interface Pod .

BS Interface Pod Module

The BS Interface Pod module, as an intermediate module for testing input/output signal transmission, mainly realizes
the expansion of the test channel between the JTAG-Control-PCI-USB controller and the BUT and the synchronization and caching of signals.
The FPGA (Altera, EP20K160EBC365-1) is the core of this circuit design. Its function is to
convert the different control signals sent by the front-stage JTAG-Control-PCI-USB controller into TAP
control signals that can be recognized by the UUT test terminal, ensuring that TDI, TCK, TMS, and TRST are accurately applied to the test end of the UUT, and at the same time returning the collected TDO
signal to the test front-end control module. The 74LVC125 (Buffer) is used to complete the signal temporary storage, and the 74LVC125 at the output stage
can also enhance the fan-out capability of the signal. The entire BS Interface Pod module adopts an anti-EMI (electromagnetic interference) shielded package, and
the front panel reserves 4 20-pin JTAG control ports. In addition, a power indicator light is designed for power-on confirmation.

Test system software design

The system software was developed in Windows XP environment using Visual C++ 6.0 and National Instruments'
LabWindows 6.0 integrated development environment. Visual C++ 6.0 can provide a wealth of Windows program development
functions, with strong flexibility and high programming efficiency; LabWindows 6.0 provides a variety of interface protocols, rich controls and instrument drivers
, and its support for virtual instrument technology is unmatched by other development environments. At the same time, it provides a wealth of software package interfaces
, which greatly facilitates software development [4].

The software design adopts the software modularization and top-down design principles. First, the circuit modules are divided according to the MERGE principle, and
the test program is divided into different test modules. Secondly, the standard test module is constructed by macro and the module interface is optimized. Then,
other modules to be tested are effectively linked with the module interface, and then they are compiled and debugged separately. Finally, they are merged together to build
a complete test body. During the development process, dividing the software into several modules not only reduces the workload of the software, but also
encapsulates the common parts of the functions into classes, improves the reusability of the modules[5], and improves the testability of the software itself. The system
software flow is shown in Figure 4.

Test optimization

In order to reduce the probability of ATE misjudgment in fault diagnosis, the system uses weighted pseudo-random vector relationship generation and inserts interval refresh test
vectors to optimize test vectors and test processes.

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(1) Weighted pseudo-random test vector generation: Weighted pseudo-random test vector generation can achieve higher test fault coverage with shorter test code length (i.e., shorter test time). In order to shorten the test code and improve the fault coverage, this test
vector generation method can adjust the probability of generating 0 or 1 at the input end, effectively detecting difficult-to-detect faults. In the pseudo-random test code,
the probability of generating 0 or 1 at each input end is 50%.

(2) Insertion-type interval refresh: Since the data line has a certain level retention characteristic, for a group of data bus I/O
, when the BS-Cell is in the read state (such as in the Update state), the Output Enable Control
Cell of the Cell unit is in the valid state, and the test vector is applied to the I/O data bus through the BS-Cell. If the BS-Cell
is in the write state (such as in the Capture state) in the next clock beat, due to the level retention characteristic of the data line, it is possible that
the data captured and read back by the BS-Cell at this time is the Update data of the previous clock beat, causing unstable testing. The solution is that after
each read state ends, the system randomly generates a group of data different from the previous group of test vectors according to the interval time of the read state,
named *data, and performs interval refresh on the I/O bus.

Experimental results and analysis

Now, a new radar dot trace processing digital circuit is used as an example to verify the system function. The entire circuit adopts the DSP+FPGA design
architecture, and its main chips include: 5 DSPs (ADSP21060), 2 FPGAs (Atlera Flex EPF10K series
), 8 dual-port RAMs (QFP package), other E2PROM, HC244 (SOP package), HC245 (SOP package),
etc. The circuit design is complex, there are many chips, the PCB layout and wiring density is high, and the use of ICT and functional test TPS development is difficult
.

Using this boundary scan automatic test system, combined with the MERGE method, TPS development experiments and fault diagnosis were carried out on the above circuit board. The test results are shown in Figure 5.

Insert simulated fault (U8-6 stuck to 0), re-simulate: Scan chain test-->PASS-->B-Scan device cluster
Test-->PASS-->NB-Scan device cluster test-->Failed (Report: Pin(s): U3-25, R26-2, U8-6,
R26-1 possibly stuck at low, the BS nodes is U31-21(R/W)).

The above simulation results show that the board-level automatic test system based on boundary scan built by integrating the MERGE method has a
high degree of automation and accurate and effective fault isolation.

Conclusion

Boundary scan technology can realize high-speed testing of digital circuits, which can not only reduce the high fixture development cost of ICT testing and
shorten the test time, but also meet the requirements of delay fault and chip performance testing. This paper mainly aims at the problems of difficulty in implementing the test system based on boundary scan technology
and low fault coverage, and creatively proposes the MERGE method boundary scan technology. Through
in-depth research on this method, a new portable automatic test system for radar digital circuits based on this technology is constructed. After comprehensive evaluation, the system
has reliable performance, meets the requirements of maintenance and support of our army's new radar equipment, and has good development prospects. At present, the ATE is responsible for
the maintenance and support of the digital circuits of new radar equipment. Its overall design concept has important reference value and reference significance for the research and development of the same type of fault diagnosis platform
.

References:

[1] IEEE 1149.1(JTAG) Boundary-Scan Testing in Altera Devices [S]. Ver 6.0, June
2005．

[2] Jiang Anping, Feng Jianhua, Wang Xinan. Very Large Scale Integrated Circuit Testing[M]. Beijing: Publishing House of Electronics Industry; 2005.

[3] Li Xingshan, Zuo Yi, Sun Jie. Automatic Test System Integration Technology[M]. Beijing: Publishing House of Electronics Industry; 2005.

[4] Zhang Jian, Zhang Xinqin, Ren Wei, Huang Xiaogang. Implementation of a certain type of shipborne radar test system based on virtual instrument[J].
2008,16(3),346-348.

[5] Zhang Yigang, Qiao Liyan. Virtual Instrument Software Development Environment (Lab Windows/CVI6.0)[M]. Beijing: Machinery Industry Press
, 2002.