Design of Universal Ethernet Interface for Virtual Instrument Based on W3150A+

0 Introduction
Virtual instruments have quickly occupied the market with their high cost-effectiveness and strong openness, and have become a new economic growth point for measurement and control instruments. The most significant sign of entering the information age is the penetration and popularization of information networks in various industries, among which Ethernet is the most typical. As a network with low cost, high throughput, good adaptability and increasingly improved network management capabilities, Ethernet can easily integrate data acquisition systems into local area networks and even the Internet. The Ethernet bus is likely to replace other existing bus methods and become the preferred interface for virtual instrument data acquisition systems.

1 Overall design of Ethernet interface
1.1 Selection of Ethernet interface design scheme
There are usually three schemes for Ethernet interface design: one is to use FPGA to implement the description of each layer such as physical layer, network layer, access layer and transport layer. This scheme needs to implement the complex TCP/IP protocol by itself, which is difficult; the second is to realize network transmission based on physical layer network controller and microprocessor. The advantage of this scheme is strong flexibility. Different protocols can be used for different systems, which can simplify the protocol; the third is to use a dedicated protocol processing chip to realize Ethernet data transmission. The hardware circuit of this scheme is relatively simple, the development cycle is short, and there are more and more chips to choose from. It integrates multiple protocols and is very convenient to use.
This design adopts the third interface scheme, that is, a dedicated TCP/IP protocol integrated chip is used, and the control of the protocol processing chip is realized by FPGA, so as to realize Ethernet data transmission. The protocol processing chip uses W3150A+ with internally solidified TCP/IP protocol and cooperates with the physical layer chip RTL8201. The hardware circuit of this method is relatively simple and can be realized by logical hardware, making the system design simpler and more compact.
1.2 Introduction to Ethernet control chip W3150A+
W3150A+ is a TCP/IP protocol stack chip specially launched by WIZnet for Ethernet interconnection and embedded systems. W3150A+ can implement protocols such as TCP, UDP, IP Ver. 4, DHCP, ARP and ICMP. At the same time, the network interface layer (including MAC sublayer and DLC sublayer) can also be implemented in this chip. It can also provide four-way network connection. It has 16KB dual-port RAM inside that can be
used as a data buffer and supports full-duplex mode. It also has a standard MD interface that can easily connect to the physical layer interface chip. In addition, WIZnet also provides a Socket API package to accelerate the development of application programs.
Figure 1 shows the structural block diagram of the W3150A+ chip. As shown in Figure 1, W3150A+ mainly consists of 4 parts. The first part is the MCU interface. W3150A+ provides direct bus interface,
indirect bus interface and SPI bus interface. It is suitable for connecting to buses similar to 8051 microcontrollers, and is also very suitable for connecting to controllers that only have IO ports but no bus interface; the second part is the TCP/IP protocol stack. W3150A+ has completely solidified the protocols required from the MAC layer, network layer to the transport layer, so users do not need to understand the specific implementation methods and implementation codes of these protocols; the third part is the receiving and sending buffers, and the data communicated through Ethernet is exchanged through these buffers; the fourth part is the Ethernet physical layer interface (MII interface). W3150A+ can be seamlessly connected to the physical layer chip RTL8201, thereby realizing the 10/100BaseT Ethernet physical interface.

The internal registers of W3150A+ are divided into two memories and two types of registers. The two memories are used for input and output of data transmission respectively. The two types of registers are general registers and port registers. Each type of register contains a large number of status word control registers. The following briefly introduces the more important status word control registers.
Sn_MR: Port n mode register, this register is used to set the port options or protocol type;
Sn_CR: Port n command register, this register is used to set the port initialization, shutdown, connection establishment, disconnection, data transmission and command acceptance, etc.;
Sn_IR: Port n interrupt register, this register is used to display information such as establishment and termination of connection, data reception, transmission completion and time overflow;
Sn_PORT: Port n port number register, this register can set the corresponding port number in TCP or UDP mode;
S_TX_FSR: Port n transmit memory remaining space register, this register is used to indicate the size of the transmit data space that the user can use. Before sending data, the user must first check the size of the remaining space and then control the number of bytes of the transmitted data;
Sn_TX_RR: Port n transmit memory read pointer register, this register is used to indicate the current position of the port transmit memory after the transmission process is completed. When the command register of port n receives
the SEND command, it can immediately send out the data from the current Sn_TX_RR to Sn_TX_WR. After the transmission is completed, the value of Sn_TX_RR changes automatically;
Sn_TX_WR: Port n transmission write pointer register, which can indicate the address when writing data to the TX memory;
Sn_RX_RSR: Port n receive data byte number register, this register is just the number of bytes of data received by the port receive data buffer, which can usually be calculated from the value of Sn_TX_RR to Sn_TX_WR
. After writing the RECV command to the port n command register, the register value will automatically change and can receive data from the remote end;
Sn_RX_RD: Port n receive buffer read pointer register, this register is just the read address information after the port receiving process is completed.
W3150A+ has 4 independent ports (Sockets) inside, and their status and control are mapped to the second to fifth register areas respectively. It is mainly used to control the port working mode (TCP server
, TCP client, UDP or PPPOE, etc.), set the port number of the port, set the destination host IP address and port number of the port, and control the port receiving and sending data. [page]

2 Hardware Design of Ethernet Interface
The hardware design of this interface mainly includes the interface design between FPGA and W3150A+, the interface design between physical layer chip RTL8201 and W3150A+, and the design of clock module and power module. The hardware design block diagram is shown in Figure 2.

2.1 Interface design between W3150A+ and FPGA
With the rapid development of semiconductor technology, the computing power, capacity and reliability of FPGA (Field Programmable Gate Array) have been greatly improved. It is becoming a new favorite in the fields of digital circuits and digital signal processing with its highly flexible user field programming function, repeated rewritable function and high reliability.
Considering the cost, practicality and power consumption, the FPGA chip selected in this design is the EPM570GT100C4 of Altera's MAXII series. The MAXII series device is a non-volatile CPLD that uses a 0.18μm manufacturing process and contains 240 to 2210 logic units and 8Kbits of non-volatile memory. Compared with other CPLDs, it can provide fast, stable and more I/O pins.
There are three ways to interface W3150A+ with microprocessor chips: direct bus interface mode, indirect bus interface mode and SPI mode. The direct bus interface mode is suitable for large data transmission; the SPI mode has fewer interface connections and is suitable for small data volumes and relatively low transmission rates; the data transmission performance of the indirect bus interface mode is between the two
. This system uses the direct bus interface mode to maximize the data transmission rate. The specific interface circuit is shown in Figure 3.

2.2 Interface design between physical layer chip and W3150A+
RTL8201BL is a single-port physical layer transceiver with only one MII/SNI (media independent interface/serial network interface) interface. It can be used to implement all 10/100M Ethernet physical layer functions, including physical layer coding sublayer (PCS), physical layer medium connection equipment (PMA), twisted pair physical medium associated sublayer (TP-PMD), 10Base-Tx encoding and decoding, and twisted pair media access unit (TPMAU). The PECL interface can support the connection of an external 100Base-FX fiber optic transceiver. This chip is made using advanced CMOS technology and can meet the requirements of low voltage and low power consumption.
RTL8201BL and W3150A+ can be connected through a standard MII interface, where pins RX_CLK, RXDV, RXD[0:3] and COL are used for data reception, while TX_CLK, TXE, TXD[0:3] are used for data transmission. The specific circuit diagram is shown in Figure 4.

[page]

3 Data transmission implementation process
Through the controller to read and write registers, W3150A+ can connect to the network. The specific operation process is described below.
Initialization should be performed first. Initialization settings include basic settings, network information settings, port memory information settings, etc. After the settings are completed, data transmission can be performed. Data transmission can be
performed in TCP, UDP, IP_RAW and MAC_RAW modes, and the communication mode can be selected in the protocol type of the port n mode register (Sn_MR). Among them, the basic settings include the mode register (MR), interrupt mask register (SIMR), retransmission time register (RTR), retransmission count register (RGR), etc.; setting network information includes setting the gateway (GAR), setting the source hardware address (SHAR), setting the subnet mask (SUBR), setting the source IP address (SIPR), etc.; and setting the port memory information is mainly to set the size allocation of the send buffer and the receive buffer, which can be achieved by setting the RMSR and TMSR registers.
Based on the FPGA chip EPM570GT100C4, this system can use the software Quartus II to develop logic control functions to achieve control of W3150A+. Its main ports are as follows:
nrst: reset input key, low level is valid;
clk: clock input;
nwrst: reset output, which can reset W3150A+ and RTL8201;
nwr: write enable signal for W3150A+, low level is valid;
nrd: read enable signal for W3150A+, low level is valid;
ncs: chip select signal of W3150A+, low level is valid;
address: 15-bit address signal;
data: 8-bit data signal;
This interface communication design adopts UDP communication mode, and its communication flow chart is shown in Figure 5.

Port initialization mainly initializes the port, including setting UDP mode, setting port number, and setting OPEN command; the value of Sn_RX_RSR register can be used to detect whether data is received
. If it is not zero, it will enter the data receiving process; during the receiving process, first read the value of Sn_RX_RSR register, that is, the number of bytes of received data, then calculate the offset address and the actual physical address, and then
read the data according to the physical address. During the data reading process, if the physical address reaches the high limit address set by the port, first read the data at the high limit address, then change the physical address to the base address, and then continue to read the remaining data from the base address. After reading all the data, add the value of Sn_RX_RR to the length of the read data, then write sn_RX_BASE, and finally write the RECV command to the instruction register of port n.
Sending data?/The implementation process of the sending process is to first read the value of S_TX_FSR register so that the size of the sending data space can be used to calculate the offset address and the actual physical address, and then
write the data to be sent from the physical address. During the data transmission process, if the physical address has reached the high limit address set for the port, the data is first written to the high limit address, and then the physical address
is changed to the base address, and then the data is continued to be written from the base address. After writing all the data, the value of Sn_TX_WR is added to the length of the data to be sent, and then written to Sn_TX_BASE, and finally
the SEND command is written to the instruction register of port n.
The completion of the transmission can be determined by detecting the value of Sn_CR after sending the (SEND) command to determine whether all the data has been sent.
When the remote end does not exist or the data transmission is abnormal, a timeout error will occur. This time, the Sn_IR (TIMEOUT bit) can be detected to determine whether the timeout has occurred.
When all operations are completed, the window should be closed, that is, the Sn_CR register should be set to CLOSE.

4 Conclusion
This article introduces the design of the Ethernet interface and the implementation process of its data transmission. The method in this article can make the Ethernet interface run normally, so it can lay the foundation for the subsequent development of virtual instruments. In fact, this method has been proven by many experiments: it fully meets the needs of the project.