Design of Video Signal Generator Based on FPGA

0 Introduction
In optoelectronic measurement systems, image processors are required for image acquisition and processing. In order to evaluate and test the image acquisition and processing capabilities of image processors, it is often necessary to input specific videos into the image processors and perform various functional tests. At present, with the widespread application of digital cameras, image processors mostly use digital interfaces. Moreover, the detection of image processors requires that the video content generated by the signal generator is increasingly rich and the frame rate is increasingly high. However, the signal generators currently used to detect image processors are mostly standard analog video outputs, such as the analog video generators proposed in the literature. Although some of them can generate digital videos, the content is fixed. If the content is changed, the digital video signal generator needs to be reprogrammed to meet the requirements, which is troublesome and cannot meet the increasingly complex requirements. Therefore, the development of a digital video signal generator that can flexibly change the video content has become very urgent. This paper proposes a design method for a digital video signal generator, which can simultaneously obtain LVDS and CamerLink format videos for digital image processor detection. In addition to being able to be used independently without a computer, the design method proposed in this paper can also be used to change the parameters of the signal generator output video in real time without rewriting the program. Just connect the signal generator to the computer through the serial port, and you can change the target grayscale, background grayscale, target size, and target movement speed in the video through human-computer interaction. In addition, the background of the target can also be selected from the SDRAM on the board. Compared with previous video signal generators, the signal generator proposed in this paper can not only generate a variety of digital videos, but also flexibly change the parameters of the generated video, so it has certain application value.

1 Hardware composition
The digital video generator is mainly composed of FPGA module, single-chip microcomputer module, serial communication module, TTL to L,VDS module, FTL to Camera L,ink module, and SDRAM module. The whole system block diagram is shown in Figure 1.

1.1 Working Principle
Digital video signals are mainly composed of line synchronization, frame synchronization, pixel clock, and image data. The line synchronization determines the starting position of a line, the frame synchronization determines the starting position of a frame, and the pixel clock determines how many columns of image data there are in a line. According to the composition of digital images, it can be seen that if you want to generate a digital image, the above elements must be included. The relationship between the line frame signal and the image is shown in Figure 2, where VSYN represents the frame synchronization signal and HSYN represents the line synchronization signal.

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The image is collected from the rising edge of the line synchronization and then collected according to the pixel clock.
This paper designs the signal generator according to the various elements required for digital video generation. The line synchronization signal, frame synchronization signal and pixel clock are mainly generated by FPGA; the target parameters are changed through the single-chip microcomputer + serial communication module, and the changed parameters are passed to the FPGA for the FPGA to generate the corresponding motion video signal; the video data and video control signal generated by the FPGA are converted into digital video signals of LVDS and CamerLink formats through the video format conversion module.
2 FPGA control module
FPGA has the characteristics of high integration, high reliability and intelligent development tools, and is gradually becoming the ideal choice for complex digital circuit design. In addition, FPGA can realize the logical functions of hardware through programming, which greatly reduces the complexity of hardware design. Therefore, this paper uses FPGA as the core device to generate video signals. Here, the EP2C8 F25618N of the SycloncII series of ALTERA is selected, and the VHDL language is used to program and generate various signals related to digital video, and the module that communicates with the single-chip microcomputer to receive the video modification parameters and the module that obtains the internal image of SDRAM. Its structural block diagram is shown in Figure 3.

After the signal generator is powered on, the FPGA obtains the initial video parameters through the module that communicates with the microcontroller, sets the target size, target grayscale, target motion speed, and background grayscale according to the parameters, and then generates video data according to the settings. The FPGA frame synchronization module, line synchronization module, and pixel clock module generate frame synchronization, line synchronization, and pixel clock respectively, and the image data is sent out from the FPGA according to the above control signals.
In this paper, the FPGA functional modules generate frame synchronization, line synchronization, and pixel clock according to the reference clock. Here, the 50M clock is used as the reference clock signal. According to the requirements of the image processing platform for the input signal, the designed frame synchronization high level occupies 33ms, the low level occupies 1.2ms, the line synchronization high level occupies 35 μm, and the low level occupies 8.4 μm. Here, the 50M reference clock is input into the pixel clock module and is still output at a clock frequency of 50M after phase locking as the pixel clock. Since there are more rows, the limit can be performed in the program to control the number of pixels in each row. There are two main ways to generate pixels. One is to obtain the target pixel grayscale and background pixel grayscale by communicating with the microcontroller, and generate pixel data based on these two grayscales. Another way is to read the image from the SDRAM connected to the FPGA as the background, obtain the target grayscale from the communication with the single-chip microcomputer, and form pixel data together.
2.1 Single-chip microcomputer control module and communication module
In this design, the single-chip microcomputer is used as a communication management chip. It mainly realizes communication with the computer, changes the various parameters of the signal generated by the signal generator, and integrates the various parameters to the FPGA so that the FPGA can control the target's movement speed, target size, target grayscale and background grayscale according to the parameters. In order to ensure that the signal generator can be easily connected to the computer, realize human-computer interaction, change the generated video signal in real time, and start from the stable and reliable communication, the RS232 communication interface is used here. However, because the computer sends more data each time, the level conversion chip is not directly used here to connect the serial port of the computer and the single-chip microcomputer together, but a 16C650 is used to connect the level conversion chip and the single-chip microcomputer together. The advantage of this is that the 16C650 has a 32-byte FIFO inside, which can act as a data cache, so that the single-chip microcomputer can receive data stably and reliably.
2.2 Video format conversion module
Because the video signal generated by FPGA is TTL level, and the current digital video signal is mainly LVDS and CamerLink, it is necessary to perform level conversion. Here, the TTL level digital video signal generated by FPGA is connected to SN75LVDS387 to obtain LVDS video signal, and the TTL digital signal can be connected to DS90CR285 to obtain CamerLink signal. [page]

3 Software Design
The software design in this paper mainly programs the MCU and FPGA. The MCU is mainly programmed in C language, and the FPGA is mainly programmed in VHDL language. The MCU program flowchart is shown in Figure 4. The FPGA program flow chart is shown in Figure 5.

4 Conclusion
This paper introduces a digital video signal generator based on FPGA, which can generate CamerLink and LVDS video signals at the same time. At the same time, this video signal generator can change the parameters such as target, background grayscale, target size, motion speed, etc. in the generated video signal in real time through human-computer dialogue, so as to achieve the purpose of detecting the target resolution ability, target capture ability, target capture target tracking speed, target tracking accuracy and other indicators of the image processing platform. Therefore, it has certain application value.