Design and application examples of universal test system for board-level spare parts

0 Introduction

With the increasing number of spare parts for missile weapons and equipment, the testing and maintenance of various single-board spare parts delivered to the troops becomes particularly important. It is necessary to have matching electronic testing equipment to adapt to this situation. Therefore, it is considered to use an automatic testing system that integrates comprehensive measurement technology, automation technology and computer technology to reduce the difficulty and complexity of single-board spare parts testing for the troops, improve the maintenance level, and simplify and universalize the testing of single-board spare parts.

1 Design content and methods

1.1 Hardware Design Ideas

Spare parts boards can be classified based on bus and function, but due to the complexity of bus and function, they cannot be unified at present. If the test is simply classified by bus, the solution that can be adopted is to expand several buses on one motherboard to suit different interface templates. The mode block diagram is shown in Figure 1. This implementation realizes part of the function test for bus test (CPU board cannot be tested). If the test is classified by function, it is even more impossible to achieve unification.

According to the above discussion, the first thing that hardware design should do is to unify the bus interface and make it configurable. After the bus interface is unified (without considering the interface function test), the test plan can be simplified, as shown in Figure 2.

The purpose of unified bus interface: When the hardware connection is unified, the bus simulation board can realize the required bus form through programming. From the perspective of this system, the bus simulation board can realize the six buses mentioned in Figure 1. The hardware logic block diagram of the bus simulation board is shown in Figure 3.

The basic working principle of the bus simulation board is as follows: the test host sends data and commands through the "test data and command information storage unit", and the field programmable gate array (FPGA) realizes the simulation of the test bus and data after obtaining the corresponding command information. The content of the FPGA can be reconfigured online, and it can perform electrical conversion of the logic interface at any time according to the requirements of the host, and can also realize the sending of test data according to the requirements of the test host.

After the bus is unified, the next thing to consider is how to realize the interconnection of the tested templates. The unified bus interface connector defines the CPCI connector (because the test host framework is CPCI or VXI). The tested board realizes the bus interconnection through the adapter board, and the I/O interface test can be connected to each test module through the cable. The bus conversion block diagram is shown in Figure 4.

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1.2 Test system construction

1.2.1 System composition

After the bus interconnection problem is solved, the next thing to solve is how to implement the test for the dedicated template. First, a system should be built, which can cover the test of some general templates, and then the test process of the template will be introduced. The principle block diagram of the test system is shown in Figure 5.

1.2.2 Universal spare parts test system bus layout

The universal spare parts test system is designed as a 7-slot CPCI bus passive backplane. The backplane is designed with multi-layer wiring and filtering technology to improve the transmission quality of CPCI bus signals. The backplane has a total of 9 plug-in positions, including 1 power supply slot and 8 CPCI bus slots. The CPU module occupies one CPCI slot, and the two I/O test boards, analog test board, communication test board, bus simulation board, and non-bus tested board each occupy one slot. The layout of the backplane is shown in Figure 6. CN1~CN4 are used to connect the I/O part of the tested template. J2 used to connect the bus board and the adapter board is a definable simulation bus.

The test model construction is to define the bus in hardware for each test template. The purpose of defining the bus is to generate the corresponding bus when the template under test starts testing. In addition, the board logic relationship and data model are defined to facilitate the modular design of test logic. The test model is a single database unit formed for each template. Since the six bus interfaces are mentioned above, the bus interface can be implemented as a standard unit, which is convenient for subsequent board logic design. When designing the test logic of the template, you must first understand all the technical parameters and usage methods of the template, and then use the test model library and test logic library to complete the construction of the test logic. [page]

1.3 System security design

The test coverage is fully considered when designing the test system, that is, as many test types as possible should be used. Due to the above reasons, the system design is relatively complex. In order to prevent errors made by testers during use, fault tolerance and safety design must be carried out. The basic principle of safety design: the module under test cannot be damaged during the test.

After inserting the template into the test system, the first thing to do is to check whether there is a short circuit in the power supply system. In order to ensure safety, the bus type of the template must also be identified. Therefore, the system needs to design a diagnostic board. As long as the power supply of the system exists, the diagnostic board is in working state, which ensures that basic diagnostic work is completed before the test system is run.

2 Test Examples

In order to explain the above test method more clearly, the following briefly describes the test process using Advantech's standard ISA bus switch card PCL-734 as an example.

2.1 PCL-734 test model construction

First, we must understand the basic performance parameters of PCL-734. Table 1 lists the basic performance parameters of PCL-734.

As can be seen from Table 1, PCL-734 is a standard ISA bus-based output board. The test model is constructed in two steps: the first step is the bus interface design. Since the standard ISA bus is used, it can be designed as a standard unit, and the design of a single board test is no longer considered. The second step is the board test logic design. The board test logic can be completely carried out in accordance with the PCL-734 manual. The underlying driver software of the bus simulation board and the interface software of the test logic obtain the data information executed by the test software through the driver software, and then send it to the bus simulation board for execution. The bus simulation board sends the data sent by the upper layer to the PCL-734 board under test through the simulation bus (ISA here), and the board under test can achieve the agreed signal output.

2.2 Testing

After the bus signal conversion and test logic design are implemented, the signal test has become relatively easy. The signal to be tested here is the switch signal output by the OC, and the I/O test board of the test system can implement the test of this type of signal.

3 Conclusion

The board-level spare parts test system adopts mature design technology, integrates modern testing technology with computer technology, embodies the design concept of universalization, modularization and standardization, achieves the purpose of unified bus interface by realizing the configurability of the bus, and thus meets the testing needs of various computer boards and cards, and has good stability and scalability, which improves the testing efficiency of board-level spare parts, makes the testing of board-level spare parts leap to a new level, and enhances the comprehensive support capability of the troops, which is of great significance for winning the future information war under high-tech conditions.