What is a logic analyzer? - Basic knowledge of logic analyzers that you must master

So far, the term "logic analyzer" has been used loosely. In fact, most logic analyzers are a combination of a timing analyzer and a state analyzer. We will now describe the special features of each of these two analyzers.

Timing Analyzer Basics

The timing analyzer is the oscilloscope-like part of the logic analyzer. We can think of them as close cousins.

A timing analyzer displays information in the same general format as an oscilloscope, with time on the horizontal axis and voltage amplitude on the vertical axis. Because the waveforms on both instruments are related to time, the display is referred to as being in the "time domain."

Choosing the right sampling method

The timing analyzer samples the input waveform to determine if the signal is high or low. The timing analyzer is only interested in the voltage threshold defined by the user. If the signal is above the threshold when sampled, it is displayed as high or 1; below the threshold is displayed as 0 or low. From these sample points, a table of 1s and 0s is generated, representing a 1-bit image of the input waveform. The analyzer only determines if the waveform is high or low - it does not recognize intermediate levels. This table is stored in memory and can be used to reconstruct a 1-bit image of the input waveform, as shown in Figure 1.

Figure 1. Timing analyzer sampling points.

Now let's look at the display in Figure 2, where a digital oscilloscope and a timing analyzer are showing the same actual signal (a sine wave). The tendency of a timing analyzer to pull various signals into square waves may seem to affect its usability, but we should remember that a timing analyzer is not an instrument for parameter measurements. If you want to verify the rise time of a signal, you should not use an analyzer, but an oscilloscope. But if you need to verify the timing relationship between signals by observing several or even hundreds of signal lines at the same time, then a timing analyzer is the right choice.

For example, suppose we have a system in which we must refresh the dynamic RAM every 2 ms. To ensure that everything in memory is refreshed within these 2 ms, we use a counter to sequentially count and refresh all the rows of RAM. If we want to confirm that the counter has finished counting all the rows before starting again, we can set the timing analyzer to trigger when the counter starts and displays all the counts. The parameters are not of interest here—we just want to check that the counter counts from 1 to N and then starts again.

Figure 2. An oscilloscope and a timing analyzer display the same signal.

When the timing analyzer samples the input line, it gets a high or low state. If the signal line is in one state (high or low) at one sampling time and in the opposite state at the next sampling time, the analyzer "knows" that the input signal has a transition at some time between the two samples. It does not know when the transition occurs, so it places the transition point at the next sampling time, as shown in Figure 3. This causes uncertainty in the analyzer about the actual time when the transition occurs and the time when it is displayed.

The worst case for this uncertainty is one sampling period, that is, the case when the transition occurs immediately after the previous sampling point.

When using this technique, you need to make an appropriate trade-off between resolution and total acquisition time. Remember that each sample point uses one memory location. The higher the resolution (faster the sample rate), the shorter the acquisition window.

Figure 3. Timing analyzer sampling input lines

Transition sampling

When we capture data on an input line with a data burst as shown in Figure 4, we must adjust the sampling rate to a high resolution (for example, 4 ns) to capture the fast pulse at the beginning. This means that a timing analyzer with 4K (4096 samples) of memory will stop acquiring data after 16.4 µs, preventing you from capturing the second data burst.

It should be noted that in normal debugging work, we sample and capture data for long periods of time when there is no activity. They use the logic analyzer memory but do not provide more information. If we know when the transition occurs, whether it is a positive transition or a negative transition, we can solve this problem. Only storing the basic information when the transition occurs can use the memory more efficiently.

To achieve transition timing, we can use a "transition detector" at the input of the timing analyzer and the counter. Now the timing analyzer only stores those samples before the transition, and the elapsed time to the last transition. With this approach, only two memory locations are used for each transition, and no memory is required at all when there is no activity on the input.

In our example, depending on how many pulses are present in each burst, the second, third, fourth, and fifth bursts can now be captured while maintaining a high timing resolution of up to 4 ns (Figure 5).

Here we talk about "effective memory depth", which is equal to the total time data captured divided by the sampling period (4 ns).

NOTE: This is a schematic illustration of the transition timing technique.

Figure 4. High-resolution sampling

Figure 5. Sampling using a transition detector.

Glitch Capture

One of the most annoying problems in digital systems is the "glitch". Glitches are notorious for causing disastrous consequences at the most inopportune time. How do you catch a glitch that occurs only once every 36 hours and crashes your system? This is where a timing analyzer comes in handy.

The analyzer features glitch capture and triggering capabilities, making it easy to track down hard-to-find glitch problems.

Glitches can be caused by capacitive coupling between circuit board traces, power supply ripple, high instantaneous currents required by certain devices, or other events. A timing analyzer can easily identify glitches by sampling the input data and keeping track of any transitions that occur between samples. In the analyzer, a glitch is defined as any transition that crosses a logic threshold more than once between two consecutive samples (Figure 6).

As we discussed earlier, the analyzer keeps track of all transitions between samples. To identify glitches, we need to “teach” the analyzer to keep track of all multiple transitions and display them as glitches.

Displaying glitches is a very useful feature, and it also helps to provide the ability to trigger on glitches and display the data that occurred before the glitch, thereby helping us determine the cause of the glitch. This capability also allows the analyzer to capture only the data we want when the glitch occurs.

Let's recall the example at the beginning of this section. We have a system that periodically crashes because a glitch appears on one of the signal lines. Since the period is so long, even if we could save all the data (assuming we have enough storage capacity), we would have to sort through an incredibly large amount of information. Another approach is to use an analyzer without glitch triggering and press the run button on the front panel of the instrument until you see the glitch.

Unfortunately, neither of these methods are practical. If we can tell the analyzer to trigger on a glitch, it can stop after finding the glitch, capturing all the data before the glitch. We let the analyzer work first, and when the system crashes, we get a record of the data leading up to the error.

Figure 6. Burr

Triggering the Timing Analyzer

Another oscilloscope term that users are very familiar with is "triggering." It is also used in logic analyzers, but is often called a "track point." Unlike an oscilloscope trace, which always starts after a trigger, a logic analyzer captures data continuously and stops when it finds a track point. This allows the logic analyzer to display information before the track point, which is called negative time, as well as information after the track point.

Pattern trigger

Setting the tracking characteristics of a timing analyzer is slightly different from setting the trigger level and slope of an oscilloscope. Many analyzers trigger on high and low patterns that span multiple input lines.

Note the menu in Figure 7. We have told the analyzer to start capturing data when channels 0, 2, 4, 6 of "INT4" are high (logic 1) and channels 1, 3, 5, 7 are low (logic 0). Figure 8 shows the result, with the middle vertical line showing the trace point. At the trace point, channels 0, 2, 4, 6 are all high, while channels 1, 3, 5, 7 are all low.

To make things more convenient for some users, most analyzers allow trigger points to be set not only in binary (1s and 0s), but also in hexadecimal, octal, ASCII, or decimal.

If the previous example uses hexadecimal settings, the trigger characteristics can be set to 55 instead of 0101 0101. When viewing 4, 8, 16, 24, 32 bit wide buses, it is more convenient to use hexadecimal trigger points. Imagine how troublesome it would be to set a 24 bit bus in binary!

Figure 7. INT4 set to trigger on high and low patterns

Figure 8. Waveform with tracking points

Edge trigger

Edge triggering is a familiar concept to those who are used to using oscilloscopes. When you adjust the "trigger level" knob on an oscilloscope, you know that you are setting a level for a voltage comparator, which tells the oscilloscope to trigger when the input voltage crosses that level. Edge triggering on a timing analyzer is similar, except that the trigger level is preset to a logic threshold.

Why is edge triggering included in a timing analyzer? Many logic devices are level dependent, and the clock and control signals of these devices are edge sensitive. Edge triggering allows you to capture data synchronously with the device clock.

For example, consider an edge-triggered shift register that does not shift data correctly. Is this a data issue or a clock edge issue? To check this device, we need to verify the data recorded by the clock edge (Figure 9).

You can tell the analyzer to capture data on the clock edge (rising or falling) and get all the outputs of the shift register. Of course in this case we have to delay the trace points to account for the propagation delay through the shift register.