Design of a dual-channel signal generator with adjustable phase difference

Abstract: In order to adjust the phase difference between two sinusoidal signals of the same frequency, a dual-channel signal generator with adjustable phase relationship is designed using DDS technology. The output frequency range of the signal generator is 0Hz~150MHz, the frequency resolution is 1μHz, the phase adjustment range is 0%~360% and the resolution is 0.022%. It can not only output two sinusoidal signals of the same frequency and adjustable phase difference, but also can be used as two independent signal generators with adjustable frequency, amplitude and phase. 

As the most basic electronic instrument in the field of electronic technology, the sinusoidal signal generator is widely used in aerospace measurement and control, communication systems, electronic countermeasures, electronic measurement, scientific research and other fields [1-2]. With the development of electronic information technology, the requirements for its performance are becoming higher and higher, such as high frequency stability, fast conversion speed, amplitude modulation, frequency modulation, phase modulation and other functions. In addition, it is often required that the two sinusoidal signals have not only the same frequency, but also a certain phase difference. To achieve a certain phase difference between the two signals, there are usually two implementation methods: one is to use a phase shifter, such as a resistor-capacitor phase shifter network, an inductor phase shifter, an inductive voltage divider phase shifter, etc. This method has many shortcomings, such as the phase shift accuracy is greatly affected by the characteristics of the components, the phase shift accuracy is poor, the phase shift operation is inconvenient, and the phase shift angle drifts due to factors such as load and time; the other is to use digital phase shifting technology, which is the current trend of phase shifting technology [3]. The core of digital phase shifting technology is to digitize the analog signal or phase shift angle first, and then restore it to an analog signal after phase shifting. This paper uses direct digital frequency synthesis technology to design a dual-channel sinusoidal signal generator, which can output two sinusoidal signals with the same frequency and adjustable phase difference. The two channels can also be used independently to perform frequency modulation, amplitude modulation and phase modulation respectively. The signal generator has the advantages of high frequency stability and rapid frequency and phase modulation.

1 Basic Principles of Direct Digital Frequency Synthesizer 

Frequency synthesis refers to the technology of generating a large number of discrete frequencies with the same accuracy and stability through a series of arithmetic operations on a standard signal frequency. There are many ways to implement frequency synthesis. Among them, direct digital frequency synthesis technology has incomparable advantages over traditional frequency synthesis technology, such as fast frequency switching speed, high resolution, easy control of frequency and phase, etc. [4-5]. Therefore, it has been increasingly widely used and has become the first choice for frequency source design in modern electronic systems and equipment. The direct digital frequency synthesizer consists of a reference clock, a phase accumulator, a sine lookup table and a D/A converter, as shown in Figure 1. Direct digital frequency synthesis technology samples, quantizes and encodes the sinusoidal signal according to the phase interval, and then stores it in an EPROM to form a sine lookup table. During frequency synthesis, the phase accumulator counts the clock pulses under the action of the reference clock, and adds the accumulated phase output by the accumulator to the phase increment preset by the frequency control word K, and the result of the addition forms the address of the sine lookup table; the amplitude quantized sine function value in the unit corresponding to the phase in the table is taken out, and the analog signal is output through the D/A converter, and then smoothed by the low-pass filter to obtain an analog signal that meets the requirements. The maximum counting length of the phase accumulator is the same as the number of phase separation points stored in the sine lookup table. Due to the different phase increments of the phase accumulator, the number of sampling points in one cycle will be different. When the sampling frequency (determined by the reference clock frequency) remains unchanged, the frequency of the output signal will also change accordingly. If the initial phase of the accumulator is set, the output signal can be phase controlled. 

According to the sampling principle, if two identical frequency synthesizers are used, and their reference clocks are the same, and the same frequency control word and different initial phases are set, then in principle, it is possible to output two identical frequency signals with a certain phase difference. AD9852 is a highly integrated direct digital frequency synthesizer with adjustable frequency, phase, and amplitude produced by ADI. It integrates high-performance D/A converters, high-speed comparators, program registers, reference clock multipliers, and high-performance digital control units that can perform various operations, and can achieve full digital programming control. The output signal frequency control word of AD9852 is 48 bits, which makes the output frequency adjustment resolution reach 1μHz. The frequency range of the output signal can be from DC to 150MHz, the phase adjustment control word is 14 bits, the phase adjustment resolution is 0.022%, and the amplitude adjustment control word is 12 bits. The signal generator designed in this paper is based on two AD9852 chips. Figure 22 Hardware design of signal generator The signal generator consists of a computer, an interface circuit, a CPLD, a frequency synthesis chip, and a low-pass filter, and its block diagram is shown in Figure 2. The computer sends the frequency control word, phase control word, and amplitude control word to the two frequency synthesis chips AD9852 through the interface circuit and CPLD, respectively, so that it outputs a sine wave signal with a certain frequency, phase, and amplitude, and forms a smooth sine wave after passing through the low-pass filter. 

To make the phase difference between the two output signals A and B adjustable, the two signals must be synchronized, and the following conditions must be met: 

(1) There should be a small enough phase offset between the reference clocks input to the two AD9852s. This phase shift will cause a proportional phase shift between the output signals. Therefore, the wiring design must be carefully carried out to make the lead distances from the CPLD reference clock output pin to the reference clock input pins of the two AD9852s equal to ensure system clock synchronization. In addition, the jitter of the reference clock rising/falling edge should be as small as possible, and the rising/falling time should be as short as possible, because the trigger voltages of different AD9852 input circuits are different, so a long rising/falling time of the reference clock will increase the phase error of the output signal. 

(2) After the frequency control word is sent to the data buffer of AD9852, an update clock must be used to send the data in the data buffer to the phase accumulator, and then output it after it becomes valid data. AD9852 has two update clock generation methods, one is automatically generated by the chip, and the other is provided by the outside. To synchronize the two output signals, an external I/O update clock must be used, and the reference clock signal (REFCLK) and the rising edge of the external I/O update clock (UPDATE CLK) must meet the timing relationship shown in Figure 3.

The rising edge of the update clock must occur between 0.3ns after the falling edge of the reference clock and 1.5ns before the next falling edge (the dark area in Figure 3 is the valid area). This allows the two AD9852s to work under the same system clock (the reference clock multiplied by a certain multiple), and the difference in the number of their system clock pulses cannot exceed 1 pulse. 

(3) Before the first data transmission, the AD9852 must be reset to ensure that the output phase of the AD9852 is known. Because the phase output of the AD9852 is continuous, the reset signal shown can reset the phase accumulators of the two AD9852s to the COS(0) state. When new data is sent to the phase accumulator, the phase relationship between them can be maintained, and the phase difference between the two AD9852s can also be adjusted through the phase control word. 

CPLD (large-scale programmable logic device) has the characteristics of static reprogrammability or online dynamic reconstruction, so that hardware functions can be modified through programming like software, which not only makes design modification very convenient, but also greatly improves the flexibility and general ability of electronic systems. Therefore, it has become an important means to realize the integration of electronic systems today. This paper uses CPLD to realize the input interface between the computer and two AD9852 chips. The internal circuit of CPLD is shown in Figure 4. The interface part of Figure 4 AD9852 mainly consists of three latches, a D flip-flop, three OR gates, and a NOT gate. In the figure, D10~D17 is the data bus of the computer interface circuit, which is used to transmit data, address and control signals to AD9852; A10~A12 are address signals, which are used to select data latch (U1), address latch (U2) and control signal latch (U3) respectively; WR is the write control signal of the latch; CLKIN is the reference clock input, which is provided by a constant temperature crystal oscillator to ensure the smallest possible phase jitter. The output signal WR1 is the write control signal of the first AD9852, and WR2 is the write control signal of the other AD9852. RESET, UPDATE CLK, and REFCLK are the reset signals, I/O update clock signals, and reference clocks of the two AD9852s, respectively. Among them, the D flip-flop is used to realize the timing relationship between the reference clock and the I/O update clock shown in Figure 2. This paper uses direct digital frequency synthesis technology to design a dual-channel phase relationship adjustable signal generator. The output signal frequency range is DC to 120MHz, the frequency resolution is higher than 0.01μHz, and the phase adjustment resolution is 0.22%. The two channels can not only output signals of the same frequency, but also output sinusoidal signals of different frequencies, different phases, and different amplitudes. The use in the quartz crystal test system shows that this design meets the design requirements and is convenient and flexible to apply.