Design of 1553B Bus Module Fault Diagnosis System Based on Virtual Instrument

The full name of 1553B bus is "Digital Time Division Command/Response Multiplexed Data Bus", which is a serial multiplexed data bus standard. In the 1970s, the United States announced the MIL-STD-1553 standard, which was first applied to the F-16A/B fighter and became one of the main features of the avionics system of the third-generation fighter. With the improvement and perfection of technology, the MIL-STD-1553B standard was introduced after 1980. The advantages of 1553B bus in terms of high reliability and strong real-time performance make it more and more valued in modern weapon systems. At present, 1553B bus is widely used in various combat aircraft, and has also been expanded to various combat vehicles, missiles, ships and other weapon platforms.

The 1553B bus module involves many types of projects and a large number of maintenance and support. It is very difficult to quickly complete the maintenance and support of the faulty module. In order to reduce the difficulty of fault location, shorten the maintenance time, and improve the maintenance quality, it is of great significance to study the design of a universal 1553B bus module fault diagnosis system based on a universal 1553B bus module maintenance platform.

1  System structure of 1553B bus module

Analyze the system structure of the 1553B bus module, and the system structure design is shown in Figure 1. The 1553B bus module hardware mainly includes a communication controller (CPU, EPROM, RAM and clock reset circuit, which mainly undertakes the tasks of the transport layer, including controlling the 1553B protocol processor, handling communication errors, responding to system host commands for services, etc.), shared memory (DPRAM), 1553B protocol processor, dual-channel bus transceiver and isolation transformer, timer (real-time clock RTC), subsystem host interface control logic, internal control logic and serial port circuit

2 Maintenance test platform system integration

The maintenance test platform adopts the virtual instrument technology based on VXI bus. The hardware platform of the maintenance test platform system mainly consists of system controller, VXI test system, program-controlled power supply, general oscilloscope, PC-MBI module, multi-serial port card and test interface adapter. The test system composition is shown in Figure 2.

1) The system controller uses a 1394 interface card and a GPIB card. The industrial computer communicates with the bus control module in the VXI test system in a transparent manner through the 1394 interface: the GPIB interface card realizes the control of the programmable power supply and oscilloscope, and the GPIB control module embedded in the oscilloscope and programmable power supply completes command translation in a transparent manner to control the operation of the programmable power supply and oscilloscope.

2) VXI test system

In the design of the test system, the VXI bus system is the key component of the design. The test system integrates the VXI chassis, 0-slot modules, digital test subsystems and I/O modules.

a. VXI chassis: We chose the 13-slot C-size chassis E8403A produced by AGILENT.

b.0 slot module: It is the control core of the VXI bus test system. The E8491B module produced by AGILENT is selected, which includes a MODID register and a 10MHz clock source. It has a trigger function and can program 8 internal TTL trigger signals.

c. Digital test subsystem: It is composed of SR2510 with slot C size. The SR2510 module includes timing and vector control and can be equipped with 96 digital I/O channels. This maintenance platform is equipped with 64 digital I/O channels for the test module.

dI/O module: The E1458A module produced by AGILENT is used. This module is a 96-channel digital I/O module that is compatible with TTL level (0-5V) and COMS level.

3) Program-controlled power supply: AGILENT produces E3631A, the technical indicators of this power supply are as follows:

a. 2-way voltage adjustable 0～+25V/1A;

b. Voltage adjustable: 0～+6V/5A.

4) General purpose oscilloscope

The general oscilloscope is a TDS3012 series oscilloscope produced by TEK. The main technical indicators of the oscilloscope are as follows:

a. With dual channels;

b. Bandwidth up to 350MHz;

c. The sampling rate can reach 1.256G;

d. With GPIB interface.

5) Test interface adapter

The test interface design in the test system adopts an interconnection structure. A unified external test interface (main adapter) is formed, and VPC's VXI interlock receiver is selected as the signal connection adapter. Since different objects under test have different external connectors, sub-adapters are designed according to the characteristics of the objects under test. This method realizes the reuse of the resources of the entire test system and improves the scalability and versatility of the test system.

6) PC-MBI card

Simulate 1553B bus terminal to realize interface communication and protocol testing with 1553B bus module.

7)Multi-channel serial port card

CPU development debug interface or test interface on 1553B bus module.

3 Fault Diagnosis Software Design

3.1 Fault diagnosis software platform

There are two types of fault diagnosis software platforms: one is a software development platform based on virtual instruments and a user-operated human-computer interaction interface; the other is the internal CPU development environment of the 1553B bus module (186 monitoring system, CCStudio). Different development environments are used depending on the type of CPU chip used. If the CPU is 80C186, the development environment is the 186 monitoring system; if the CPU is TMS320F240 or TMS320F2812, the development environment is CCStudio.

The virtual instrument is based on LabWhadows/CVI as the software platform, which is an interactive C language development platform developed by the American NI company. The software is a powerful and flexible C language platform that organically combines professional tools for data acquisition, analysis, display and control.

3.2  Test software design

In the design of maintenance test platform, test software is the core part of the whole maintenance test platform, among which TPS (Test Program Set, TPS) design takes modularization, standardization and universalization into consideration, and can be easily ported to other 1553B bus modules of the same series. At the same time, TPS design directly affects the comprehensiveness of test coverage and whether the fault point can be accurately located.

The test software mainly includes the test of 1553B bus module communication function and each functional unit.

Analyze the design performance and functional indicators of the 1553B bus module, and divide the 1553B bus module circuit into the smallest functional unit circuit. Since the dual-port memory (DPRAM) in the 1553B bus module design is used as the data interaction interface between the subsystem host and the module communication controller, the 1553B bus module functional unit is divided into four parts, the first part is the module communication controller circuit test; the second part is the subsystem host interface circuit test; the third part is the 1553B protocol interface circuit test; the fourth part is the reset circuit test, as shown in Figure 3.

The communication controller circuit test includes: EPROM functional unit circuit test, RAM functional unit circuit test, CPU control DPRAM (right port) circuit test, interrupt controller, timer functional circuit test and reset RTC counter functional circuit test.

Subsystem host interface circuit test includes: RTC functional unit circuit test, DPRAM (left port) circuit test.

The above functional units constitute the test subset for locating each fault of the 1553B module.

3.2.1 ERROM test

The data in the E]PROM is read and verified, and the verification value is compared with the checksum. If they are consistent, the E]PROM function is normal.

3.2.2 RAM functional unit test

A typical test data method is used, including the following test data: step 1, 0x0000, ox5555, 0xaaaa, 0xffff and the memory cell write unit address value. This test method fully tests the RAM memory bank, and at the same time effectively tests the RAM address bus and data bus, such as whether the bus is short-circuited or open-circuited. [page]

3.2.3 DPRAM (right port) functional unit test

A typical test data method is used, including the following test data: step 1, 0x0000, ox5555, 0xaaaa, 0xffff and memory cell write unit address value. This test method fully tests the memory bank of the DPRAM and effectively tests the address and data bus of the DPRAM, such as whether the bus is short-circuited or open-circuited.

3.2.4 Interrupt control function unit test

By simulating the subsystem host interrupt signal and clearing the host interrupt signal in the development environment, the subsystem host's read interrupt signal status is simulated. If it is consistent with the setting, the function is normal.

3.2.5 Timer function unit test

The test platform is equipped with an oscilloscope to collect the output signal of the timer circuit and measure the timer output waveform. If the output is according to the expected value, the timer function is normal.

3.2.6 Reset RTC counter function circuit test

Access the specific I/O space unit through the development environment to clear the RTC to 0, and then read the RTC value through the simulation subsystem host access. If it counts from 0, the CPU clear RTC counter function circuit works normally.

3.2.7 Accessing the RTC Function Unit Circuit Test

The analog subsystem host sets the value of the RTC counter and then reads back the RTC value. If the RTC value is counted based on the set initial value, the analog subsystem host accesses the RTC functional unit circuit and works normally.

3.2. 8 DPRAM (left port) functional unit test

A typical test data method is used, including the following test data: step 1, 0x0000, ox5555, 0xaaaa, 0xffff and memory cell write unit address value. This test method fully tests the memory bank of the DPRAM and effectively tests the address and data bus of the DPRAM, such as whether the bus is short-circuited or open-circuited.

4. Fault diagnosis based on fault tree

4.1 Fault model establishment

The fault tree model is a behavioral model based on the structure and characteristics of the object being diagnosed. It is a qualitative causal model that takes the least desirable event of the system as the top event, other events that may cause the top event as the intermediate events and bottom events, and uses logic gates to represent the connections between events. It reflects the entire logical relationship between the feature vector and the fault vector (fault cause). In fault tree analysis, tree building is a key and basic step. Whether the tree building is perfect will directly affect the accuracy of the analysis and diagnosis results. The key to tree building is to clearly understand the logical relationship of the system function being analyzed, as well as the failure mode, impact and fatality. Whether the tree building is perfect directly affects whether the qualitative analysis and quantitative calculation results are correct.

4.1.1 Principle Analysis

The design principle of the 1553B bus module is shown in Figure 4. The 1553B interface circuit interacts with the subsystem host through DPRAM (dual-port memory). The subsystem host does not directly control the 1553B interface protocol chip. The communication controller (CPU, etc.) reads the subsystem host command word in DPRAM to configure the working state of the 1553B protocol chip. The protocol chip receives the 1553B bus command and obtains the internal bus control right through DMA, writes the received data into DPRAM or reads the sent data from DPRAM.

4.1.2  Fault tree establishment

The main function of the 1553B bus module is to realize the data communication function of the 1553B bus interface. Taking the 1553B bus communication failure (data transmission error, bus non-response failure, host command non-response) as an example, the main factors affecting the normal communication of the 1553B bus are analyzed: the subsystem host correctly sets the command word; the communication control correctly executes the subsystem host setting the command word; the communication controller correctly sets the 1553B protocol processor; the 1553B protocol processor DMA mode works normally; the 1553B transceiver transformer normally generates the Manchester code signal. The above fault influencing factors are combined to construct the 1553B bus communication fault tree. See Figure 5.

4.2 Fault Diagnosis Example

According to the fault model, fault detection and troubleshooting are carried out based on the maintenance test platform, and statistics are made based on maintenance cases and data. The troubleshooting process is compiled according to the probability of failure, and the fault points with high failure rates are troubleshooted first. Taking the corrective maintenance of the 1553B bus module as an example, the fault phenomenon of the 1553B bus module "not responding to the subsystem host command" is selected to describe the fault isolation steps.

The fault phenomenon is: the 1553B bus module did not respond to the subsystem host command during initialization.

There are two main reasons for this failure: first, the subsystem host did not correctly write the host command word into the DPRAM memory; second, the communication controller did not correctly respond to the host command.

Comprehensive analysis of maintenance data over the years shows that the most likely cause of failure is that the subsystem host fails to write the command word correctly. Taking this cause as an example, the factors that cause the failure are as follows: failure of the subsystem host to access the DPRAM logic chip; failure of the subsystem host bus driver chip; breakage of the subsystem host access DPRAM signal printed circuit board.

5 Conclusion

Based on the research and summary of the system structure and working principle of the 1553B bus module, this paper designs a universal 1553B bus module maintenance test platform, establishes a fault model, and in accordance with the S1000D standard, informatizes the fault phenomenon, fault diagnosis and fault location methods to form a fault diagnosis expert database. Through a good user interaction platform, it is applied to the 1553B bus module fault diagnosis process and guides the 1553B bus module maintenance work, which has a positive significance for improving maintenance efficiency and quality.