Application of high-performance line cards for synchronous networks

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Application of high-performance line cards for synchronous networks [Copy link]

 

In a distributed network, the uncertainty of network transmission delay leads to poor synchronization accuracy when triggered by network commands. At the same time, due to the dispersion of the locations of nodes in a distributed network, it is not suitable to use hardware synchronization of each node to provide high-precision synchronization triggering. The synchronization triggering method based on time information is particularly suitable for distributed long-distance synchronization systems. Its triggering method is flexible and not limited by distance.

Synchronous Ethernet is a technology that uses Ethernet link code stream to recover the clock, referred to as SyncE. Synchronous Ethernet achieves network clock synchronization by recovering the sender's clock from the serial data code stream. However, SyncE cannot provide time synchronization. IEEE1588v2 is a unified method for providing time synchronization and frequency synchronization. It can be suitable for time and frequency transmission on different transmission platforms. It can transmit frequency in a one-way manner based on the 1588v2 timestamp in a packet-based time transfer (TOP) mode, and can also use the IEEE1588v2 protocol to achieve time synchronization. The core idea of IEEE1588v2 time synchronization is to use the master-slave clock method to encode time information, use the network's symmetry and delay measurement technology, and achieve master-slave time synchronization through two-way interaction of message messages.

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Clock transfer system for synchronous network

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The line card clock solution must be able to automatically select the appropriate reference clock input and perform the master and slave clock switching as smoothly as possible to avoid causing transient jumps in the output clock. At the same time, the clock must meet the requirements for clock jitter in various working modes of the line card to ensure the bit error rate of the service link.

The frequency control circuit of the line card will select the main reference frequency of the line card based on the priority; if the main reference frequency fails, the frequency control circuit of the line card will switch to the backup reference frequency. The phase difference between the main reference frequency and the backup reference frequency may cause a sudden phase change at the output of the clock and affect the system performance, such as an increase in the bit error rate. Therefore, the system has extremely strict requirements on the frequency output phase jitter change rate caused by the reference frequency switching process. For example: SONET stipulates that the maximum peak-to-peak change of the frequency output phase must be less than the maximum time interval error MTIE specified by GR-1244-CORE.

In addition, the system requires that the line card can manually or automatically switch between the primary reference input frequency and the backup reference frequency when the input reference frequency fails. Automatic switching can include a recovery function, in which the system switches to the backup reference frequency when the primary reference frequency fails, and then switches back to the primary reference frequency after the primary reference frequency returns to normal. Automatic switching can also not include a recovery function, in which case the system switches from the primary reference frequency to the backup reference frequency and continues to use the backup reference frequency even if the primary reference frequency returns to normal.

The following table lists the reference clock requirements for different trace and cable lengths in a 56G PAM-4 link. As can be seen, the switch ASIC vendor for 56G PAM-4 SerDes requires a maximum reference clock jitter of 150 fs RMS in the frequency band from 12 kHz to 20 MHz.

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The total allowed jitter in a serial link is determined by the IEEE protocol or the CEI protocol. For example, IEEE 802.3bs specifies in 400GAUI-8 that for chip-to-chip (C2C) data transmission, the maximum transmit jitter (RMS) should be no greater than 0.023UI, which is equivalent to a total link jitter of 865 fs RMS. The jitter allocated to the clock module is usually low, even as low as 10% total jitter for PAM-4 systems where the SNR is usually low. Therefore, for a 10% clock jitter budget, the allowed reference clock jitter is 270 fs RMS.

TI's LMK05318 is a high-performance network synchronizer clock device that provides jitter removal, clock generation, advanced clock monitoring and excellent hitless switching performance to meet the stringent timing requirements of communication infrastructure. The device uses TI's proprietary bulk acoustic wave (BAW) VCO technology to generate an output clock with 50fs RMS jitter, independent of the jitter and frequency of the XO and reference inputs. The DPLL supports programmable loop bandwidth for jitter and drift attenuation, while the two APLLs support fractional frequency conversion, allowing flexible clock generation. Synchronization options supported by the DPLL include hitless switching with phase cancellation, digital holdover, and DCO mode with frequency steps less than 0.001ppb (parts per billion) for precise clock control (IEEE 1588 PTP slave operation). The DPLL can phase lock to a 1 PPS (pulse per second) reference input and supports an optional zero-delay mode on one output for deterministic input-to-output phase calibration with programmable offset voltage. An advanced reference input monitoring block ensures robust clock failure detection and helps minimize output clock glitches when loss of reference (LOR) occurs.

The figure below shows the output phase noise of LMK045318. The clock output frequency is 156.25 MHz. In the integration range (12 kHz to 20 MHz), the average jitter is 59 fs, and the PLL1 is 2.5 GHz BAW. The jitter performance can well meet the jitter requirements of the high-speed line card clock solution.

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With the phase cancellation function, LMK05318 has the industry-leading ±50ps phase transient switching. The figure below shows the switching performance when the 156.25MHz clock output is manually forced to switch from the main reference to the backup reference. It can be seen that it fully complies with ITU-T G.8262 requirements.

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Texas Instruments' DPLL (digital PLL) chip LMK05318 for IEEE1588 and synchronous Ethernet is designed to achieve synchronization throughout the packet switching network. For IEEE1588 applications, the embedded DCO (digitally controlled oscillator) can be used as a low-jitter synthesizer to complete the IEEE1588 clock recovery algorithm. For synchronous Ethernet applications, the DPLL complies with the ITU-T recommendations for EEC (synchronous Ethernet equipment clock); these devices also meet SONET/SDH synchronization requirements. TI's DPLL can switch between IEEE1588 DCO and SyncE modes and provides the following functions: selectable loop filter, delay, uninterrupted reference switching, phase slope limit and clock redundancy. These features greatly simplify the design of synchronous network service line card clocks.

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Thanks for sharing!