Measurement technology for electrical properties of nanodevices

As nanotechnology advances, research has progressed to the atom-by-atom molecular level, creating new structures with entirely new properties. In particular, the field of nanoelectronics is developing rapidly, with potential impacts across a wide range of industries. Current nanoelectronics research focuses on how to exploit carbon nanotubes, semiconductor nanowires, molecular organic electronics, and single-electron devices.

However, these tiny devices cannot be tested using standard test techniques for a variety of reasons. One of the main reasons is the physical size of these devices. The nanoscale dimensions of some new "super-CMOS" devices are so small that they are easily damaged by even the small currents used in the measurement process. In addition, traditional DC test techniques do not always reveal how the device actually works.

Pulsed electrical testing is a measurement technique that reduces the total energy consumption of a device. It does this by reducing Joule heating effects (such as I2R and V2/R) to avoid potential damage to small nanodevices. Pulse testing uses a sufficiently high power supply to apply short pulses to the device under test (DUT) to generate a high-quality, measurable signal, and then removes the signal source.

Through pulse testing, engineers can obtain more device information and more accurately analyze and understand the device's behavioral characteristics. For example, pulse testing techniques can be used to perform transient tests on nanodevices to determine their transfer functions and thus analyze the characteristics of the material under test. Pulse testing measurements are also necessary for devices with constant temperature constraints, such as SOI devices, FinFETs, and nanodevices, to avoid self-heating effects that can mask the response characteristics of interest to researchers. Device engineers can also use pulse testing techniques to analyze charge trapping effects. Charge trapping reduces drain current after the transistor is turned on. As charge is gradually trapped in the gate dielectric, the threshold voltage of the transistor increases due to the increase in the built-in voltage of the gate capacitance; thus, the drain current is reduced.

There are two different types of pulse testing: applied voltage pulses and applied current pulses.

Voltage pulse testing produces pulses with much narrower widths than current pulse testing. This feature makes voltage pulse testing more suitable for thermal transport experiments, where the time window of interest is only a few hundred nanoseconds. The amount of energy dissipated on the nanodevice can be controlled by high-precision amplitudes and programmable rise and fall times. Voltage pulse testing can be used for transient analysis, charge trapping, and AC stress testing in reliability testing, and can also be used to generate clock signals to simulate repetitive control lines, such as memory read and write cycles.

Current pulse testing is very similar to voltage pulse testing. In it, a specified current pulse is applied to the DUT and the voltage generated across the device is measured. Current pulse testing is often used to measure lower resistances or obtain the IV characteristic curve of a device without causing a large amount of energy consumption in the DUT to damage or destroy the nanodevice. Both

voltage and current pulse testing have many advantages, but their disadvantages are different. For example, the speed characteristic analysis of ultra-short voltage pulses belongs to the field of radio frequency (RF), so if the test system is not optimized for high bandwidth, it is easy to introduce errors in the measurement process. There are three main sources of error: signal loss caused by cables and connectors, loss caused by device parasitics, and contact resistance. The

main problem with current pulse testing is the slow rise time, which can be as long as hundreds of nanoseconds. This is mainly limited by the inductance and capacitance in the experimental configuration. (end)