PCIE3.0 transmitter physical layer test

1. PCIE 3.0 and PCIE 2.0

The main difference between PCIE 3.0 and its predecessor PCIE 2.0 is that the rate is increased from 5GT/s to 8GT/s. In order to ensure data transmission density, DC balance and clock recovery, PCIE 2.0 uses 8B/10B encoding, that is, every 8 bits of valid data are encoded as 10 bits of data for transmission, so that 20% of the information in the link will be invalid, that is, the maximum transmission capacity of the link is discounted by 20%. The purpose of the rate increase is to transmit data faster, and the encoding method is also indispensable. Therefore, in PCIE 3.0, 128B/130B encoding is also used (the amount of invalid information is reduced to 1.5625%), and scrambling is used (that is, the data stream is first XORed with a polynomial to obtain a more random data, and the same polynomial is used to recover it at the receiving end) to achieve data transmission density, DC balance and clock recovery. Another difference is that the PCIE 3.0 specification has required receiver testing as a mandatory test item, while PCIE 2.0 is an optional test item. The following table compares the main differences between PCI Express 2.0 and PCI Express 3.0.

2. PCIE 3.0 transmitter physical layer test

The PCIE 3.0 transmitter test items, as shown in the figure below (test items included in LeCroy's consistency test software), are the transmitter test items specified in the PCIE 3.0 CEM specification (Ver0.3) and the PCIE 3.0 basic specification (Rev3.0, Ver0.9).

1.TxEQ Preset Test (Test 1.1)

Since the rate of PCIE 3.0 has reached 8Gb/s, and the transmission channel often needs to go through the motherboard to the board, the entire link will be relatively long, which will cause a relatively large loss of high-speed signals. In order to compensate for the loss of the channel and ensure that the signal eye diagram at the receiving end can be opened, it is very necessary to use corresponding emphasis (de-emphasis or pre-emphasis) and equalization technology. Therefore, PCIE 3.0 uses de-emphasis and preshoot functions at the transmitting end.

Since the length of the PCIE 3.0 signal transmission channel is different in different designs or different products, in order to cope with more complex situations, the PCIE 3.0 specification stipulates that the transmitter can implement 11 levels of de-emphasis and preshoot functions.

The PCIE 3.0 specification specifies these 11 levels of de-emphasis and preshoot functions, so the PCIE 3.0 transmitter test needs to test these 11 types of pre-emphasis and equalization, that is, verify the de-emphasis and preshoot capabilities of the transmitter chip to ensure that it can meet the requirements of the specification. The following figure shows the definition and calculation method of De-emphasis Preshoot and Boost.

Table 4-16 below shows the coefficients and de-emphasis and pre-shoot levels for Preset 0 to Preset 10 from the PCIE 3.0 specification. [page]

In fact, the de-emphasis and preshoot functions of PCIE 3.0 are implemented through a third-order FIR filter.

Since both C-1 and C+1 are less than 0, it means that de-emphasis and preshoot act on the switching bit respectively: de-emphasis only works when the current bit of the signal code pattern switches from 0 level to 1 level or from 1 level to 0 level compared with the previous bit; preshoot only works when the current bit of the signal code pattern switches from 0 level to 1 level or from 1 level to 0 level compared with the next bit; for example, if C-1 is zero, then only De-emphasis should work; if C+1 is zero, then only Preshoot should work; if both work at the same time, Boost will be generated, that is, simultaneous switching of 0 level, 1 level, and 0 level will be generated.

The figure below shows the TxEQ Preset test results of PCIE3.0 based on LeCroy oscilloscope and its QPHY-PCIE 3.0 automated test software: each column in the figure clearly indicates whether it passes, test items, current measurement values, and specification requirements.

The test point of the Preset test of PCIE 3.0 TxEQ is selected at TP1, which is the adapter after the Breakout Channel. There is a button on the fixture that can be used to switch Preset0-Preset10. During the test, switch the button on the fixture according to the prompt of the Qualify automation software to output the corresponding signal pattern required for the oscilloscope test, as shown in the following figure:

The test pattern of the Preset test of TxEQ of PCIE 3.0 selects the pattern of the first module in the PCIE 3.0 consistency test pattern, that is, 64 consecutive 1-level and 64 consecutive 0-level patterns, and selects the 57-62UI interval of 1-level to be equivalent to 1-level and the 57-62UI interval of 0-level to be equivalent to 0-level.

2. Transmitter voltage swing without equalization (Vtx-fs-no-eq, Test 1.2)

Use the waveform of Preset4 (de-emphasis=0, preshoot=0) for testing. The test connection diagram, test points, and test pattern selection are the same as the TxEQ Preset test. The following figure shows the Vtx-fs-no-eq test results of LeCroy and the automated test software QPHY-PCIE3.0:

3. Full voltage swing and reduced voltage swing of EIEOS sequence pattern (Vtx-eieos-rs/fs limits, Test 1.3)

EIEOS (Electrical Idle Exit Ordered Set) is used to indicate the exit of electrical idle (Electrical Idle Exit). The specific code is K28.5 code, which is 8 consecutive 1 levels and 8 consecutive 0 levels repeated alternately. The total length of the code is 128 bits. [page]

The full voltage test of the EIEOS sequence (Vtx-eieos-fs) requires the Preset to be set to 10, which is the strongest boost condition, to test the voltage swing.

The reduced voltage swing test of the EIEOS sequence (Vtx-eieos-rs) requires the Preset to be set to 1, a weaker equalization setting, to verify that the smaller amplitude EIEOS pattern can also be recognized.

The EIEOS test is measured at the Tx pin, so the attenuation caused by the breakout channel needs to be considered, that is, the impact of the breakout channel needs to be eliminated by de-embedding, and the breakout S parameters need to be provided in advance. The following figure shows the test results of Vtx-eieos-rs/fs limits of LeCroy and automated test software QPHY-PCIE3.0:

4. 8GT/s Compliance Eye Test (Compliance Eye 8GT/s, Test 1.4)

The purpose of this test is to verify whether the eye height and eye width of the signal eye diagram of the system under test meet the requirements of the CEM specification. The code pattern used is the compliance test pattern of the 128B/130B encoding format. Since there are 11 presets for the Tx transmitter waveform, the CEM specification requires that only one preset code pattern (the best code pattern can be selected) must pass. You can arbitrarily select a code pattern with preset equal to 1, 7 or 8 for testing. If the code patterns corresponding to the three presets cannot pass, then you need to continue to measure the code patterns corresponding to the remaining presets until one passes. Otherwise, you need to test all the code patterns corresponding to the presets to determine whether the eye diagram test passes. The specification requires the oscilloscope to collect at least about 1.5M UIs (bits) for testing at a time. If the oscilloscope sampling rate is set to 40GS/s, you need to collect about 8M data points for testing.

The test point is selected at TP1. The test requires the use of the equalization settings at the receiving end, that is, the CTLE and DFE need to be turned on. In the LeCroy oscilloscope, the Eyedoctor II can be used to implement CTLE and DFE equalization, and the serial data analysis software SDA III can be used to perform eye diagram testing.

Since the specification also recommends using Intel's Sigtest software to implement CTLE, DFE, and eye diagram test functions, LeCroy's Sigtest software has been integrated into LeCroy's oscilloscopes. Together with LeCroy's Qualify software, it can realize automated testing of all projects and automatically generate reports in multiple formats.

5. 8GT/s Tx Jitter Parameters Test 1.5

Jitter test is a must-test item for high-speed serial signals. This test is to measure the jitter of PCIE GEN3 at 8Gb/s. The test pattern selects the compliance test pattern (compliance pattern) of the optimized 128B/130B encoding format. The test point is selected at TP1, and the influence of the breakout channel needs to be eliminated (De-embedding); all channels need to have output during the test; when de-embedding the breakout channel, the cutoff bandwidth needs to be set within the range of 8GHz-12GHz (or limit the maximum boost value), because de-embedding may amplify noise.

The jitter parameters that need to be tested for PCIE GEN3 are:

Ttx-ddj: the absolute value of the maximum data-dependent jitter minus the minimum data-dependent jitter, DDJ(max)-DDJ(min); Ttx-utj: the total jitter that is not data-dependent, defined based on the Q-Scale curve.

Ttx-udjdd: Data-independent intrinsic jitter, defined based on the Q-Scale curve.

Ttx-upw-tj: Data-independent overall pulse width jitter.

Ttx-upw-djdd: Data-independent intrinsic pulse width jitter.

For detailed definitions of the above jitter parameters, please refer to: 4.3.3.10.5-4.3.3.10.7 of PCI_Express_Base_r3.0. The following figure shows the results measured by LeCroy oscilloscope:

6. 8GT/s transmitter signal general parameter test (UI, Vtx-cm-ac-pp, Vtx-dc-cm, Ltx-Skew, Test 1.7)

This project tests the general parameters of the signal at the transmitting end. One is the UI, i.e. the bit rate test. This test requires the SSC to be turned off. The other two are Vtx-cm-ac-pp, i.e. the peak-to-peak value of half the sum of the two differential signals, and Vtx-dc-cm, i.e. the DC common mode voltage. These two parameters require a data volume of at least 1M UI. The test position is selected on the Tx chip pin. This can be achieved by testing at the TP1 position and de-embedding the Breakout channel. Ltx-Skew is the time offset between two links in a link. The following figure shows the test results of the LeCroy oscilloscope.