Design of a timing signal generation circuit on an OTP memory chip

Dynamic memories such as DRAM and SDRAM generally have clock pins, and their internal timing circuits are driven by external clock signals. For memories without clock signals, their internal timing must be generated inside the chip, which is usually the case with OTP memories (One Time Programable, OTP).
This paper proposes an on-chip timing signal generation circuit for 128 Kbit OTP memories. The timing generation circuit consists of an address transition detection (ATD) circuit and a pulse width adjustment circuit. The ATD circuit generates a pulse waveform inside the chip, and then the pulse width adjustment circuit generates a timing signal with a moderate width. This signal can be used as a control signal source for the internal timing of the memory. For example, using this signal as a control signal source, the corresponding control signal can be derived through simple delay, AND, OR operations. These signals can be used to control various functional modules inside the memory, such as sensitive amplifiers, latches, etc. In addition, the effective width of the signal source can be easily adjusted, which is better than the traditional width adjustment method.

1 Circuit structure and working principle
1.1 ATD circuit
The ATD circuit is actually an edge detection circuit. The ATD circuit detects the state of a signal or a group of signals (such as the address bus). As long as one of the detected signals undergoes a flip change, the ATD circuit will output a pulse. The width of the output pulse is determined by the parameters of the ATD circuit. Since we want to detect the change of the address line, the change of the address line includes flipping from low to high and from high to low, so it is necessary to detect the rising edge and falling edge of the address line.
The ATD circuit designed in this article can detect two changes on the address line. It is a double-edge detection circuit, and the circuit structure is shown in Figure 1. The ADDRESS port is the address signal input, and the ATD OUT port is the detection circuit output.

If the address input of the ADDRESS terminal does not change, the ATD_OUT output is always high level;
if the address input of the ADDRESS terminal changes, whether it changes from 0 to 1 (rising edge) or from 1 to 0 (falling edge), due to the existence of the delay unit, the signal reaching the input terminals A and D of the AND-OR gate in the figure will lag behind the signal reaching the input terminals B and C by the propagation delay time of the delay unit, thereby generating a low level pulse after passing through the AND-OR gate, and the pulse width is determined by the propagation delay of the delay unit. The simulation results of the ATD circuit are shown in Figure 4. As can be seen from Figure 4, after each changing edge of the input ADDRESS terminal signal, a low level pulse signal (ATD_OUT signal in Figure 4) will be generated.
1.2 Pulse width adjustment circuit
The pulse signal generated by the ATD circuit has a width of only 2.5ns and cannot be used directly to control the internal circuit, because the internal timing control signal generally requires a specific effective level width. It must first be adjusted in width to generate a signal with a width that meets the requirements.
The traditional circuit for adjusting the width is generally implemented by delay, as shown in Figure 2. E and F are the input waveform and the waveform after the delay unit, respectively. OUT is the waveform after width adjustment. The maximum width of OUT's high level is no more than twice the width of the input signal IN, because E and F must have overlapping parts (circled parts in the figure), otherwise the purpose of width adjustment cannot be achieved. This method is not flexible. If a signal with a width of twice that of the input signal IN is needed, it is difficult to implement.

The pulse width adjustment circuit designed in this paper is shown in Figure 3. ATD_OUT is the low-level pulse output signal of the ATD circuit, EN is the enable signal, and WOUT is the pulse output signal after width adjustment. [page]

When EN is low, the ATD_OUT signal is shielded and the pulse width adjustment circuit does not work;
when EN is high, but there is no low-level pulse input to ATD_OUT (that is, the address signal does not change), the pulse width adjustment circuit does not work;
when EN is high and there is a low-level pulse input to ATD_OUT (that is, the address signal changes), the pulse width adjustment circuit works normally. The following introduces its working principle, N0~N8 represents NMOS tubes, and P0~P6 represents PMOS tubes.

First, when EN is high and a low-level pulse is input to the ATD_OUT port, a low-level pulse signal is displayed on NET0. When the low level arrives, P0 and P1 are turned on first, and NET1 and NET2 are pulled to VDD, so that N2 and N4 are turned on, thereby pulling WOUT and NET3 to GND, forcing the N6 tube to be turned off; at the same time, the low-level pulse on NET0 passes through the inverter INV0 to make NET4 a high-level pulse, forcing N8 to turn on a high-level pulse width time (here 2.5ns), and pull NET5 to GND; because P6 is normally open, as long as the N6 tube is turned off, the potential of NET5 will gradually rise, so N8 is added to discharge NET5.

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Second, after the low-level pulse ends, ATD_OUT becomes high-level. At this time, NET0 is high-level, P0 and P1 are turned off. NET4 is low-level, N8 is turned off, and MOS tube P6 charges MOS capacitor N7 and parasitic capacitor on NET5. The potential of NET5 gradually rises from GND. When the potential on NET5 rises above the switching threshold VM of inverter INV1 (assuming that the time required for this process is T, the size of T determines the pulse width of WOUT), the output of inverter INV1 flips from high to low, and the output of inverter INV2 flips from low to high. The potential of NET6 is instantly raised to VDD, forcing N0 and N1 to turn on, thereby pulling NET1 and NET2 from the previous VDD to GND, forcing P3 and P5 to turn on, pulling NET3 and WOUT back from the previous GND to VDD, turning on N6, clearing NET5, and preparing for the arrival of the next low-level pulse; so far, a complete operation of adjusting the low-level pulse width has been completed.
The pulse width of the output WOUT is mainly determined by the time required for the MOS tube P6 to charge the parasitic capacitance and MOS capacitance on the connection NET5 to a potential above the switching threshold VM of the inverter INV1.

2 Charging time T
The following is the expression for the charging time T for the potential on NET5 to rise from 0 to VM:
Assume that the width-to-length ratios of the PMOS tube and the NMOS tube of the inverter INV1 are (W/L)p and (W/L)n respectively, and the switching threshold of the inverter is defined as the point where Vin=Vout. At this point, both the PMOS and NMOS tubes satisfy VGS=VDS and are in the saturation region. According to the saturation region current equation, the current of the PMOS tube is equal to the current of the NMOS tube. Ignoring factors such as the channel length modulation effect, we can get

As long as the width-to-length ratio of the PMOS tube and the NMOS tube is known, r can be calculated, and then VM can be calculated; conversely, if the value of VM we need is determined in advance, the size of the inverter PMOS tube and NMOS tube can be calculated by equations (1) and (2). For example, if we need a symmetrical inverter INV1, we hope that the value of VM is exactly VDD/2. From formula (1), we can get the value of r to be approximately 1.
Assuming that the width-to-length ratio of the N7 tube is Wn7/Ln7, the capacitance per unit area of ​​the gate oxide is Cox=εox/tox, and the sum of the gate-source and gate-drain cover capacitances of N7 is 2CoxxdWn7, where xd is a parameter determined by the process. To ignore the effect of the gate voltage VGS of N7 (i.e., the voltage on NET5) on its gate capacitance, the gate capacitance Cg7 of N7 is obtained as

follows: Assuming that the gate capacitance of the inverter INV1 is CgINV1, the value of CgINV1 can be calculated by substituting the above method into the size of the inverter.
Assuming that the drain junction capacitance of the N6 tube is CjN6, the value of CjN6 can be calculated by the drain junction area during the layout realization of the N6 tube and the junction capacitance per unit area parameter of the process.
The total parasitic capacitance Ctotal on the connection NET5 is

Assuming that the width-to-length ratio of P6 is Wp6/Lp6, the threshold voltage is VT, and the potential on NET5 gradually rises from 0 due to the charging of P6.
When the potential VNET5 of NET5 satisfies VNET5≤|VT|, P6 works in the saturation region, and the charging current Ichg1 is the saturation region current of P6 When

the potential VNET5 of NET5 satisfies |VT|
By adjusting the size of N7 and P6, the size of the capacitance or the charging current can be adjusted respectively to achieve the purpose of adjusting the time T, and the size of the time T is directly reflected in the pulse width of the output WOUT of the circuit; that is, by adjusting N7 and P6, the pulse width of the output WOUT can be controlled. No matter what kind of pulse width WOUT is required, it can be achieved by controlling N7 and P6. [page]

Under TSMC 0.18μm process, the simulation results of the overall circuit are shown in Figure 4. When the low level of ATD_OUT arrives (at the vertical line mark in Figure 2), as analyzed in Section 2.2 above, WOUT becomes low level; when the low level of ATD_OUT ends, that is, the rising edge arrives, the parasitic capacitance on NET5 is charged, and it can be seen from Figure 4 that the potential of NET5 gradually rises; when it rises to the switching threshold VM of the inverter INV1, it can be seen from Figure 4 that NET6 flips from low to high; it can be seen from the figure that NET6 flips from low to high to pull WOUT high; at the same time, NET3 is also pulled high, forcing N6 to turn on and clear NET5. It can be seen from Figure 4 that NET5 is instantly pulled low after being charged to VM, and NET6 also instantly becomes 0. It can be clearly seen from the simulation results of Figure 4 that the width of WOUT is mainly determined by the charging time T of NET5 (plus the width of ATD_OUT itself). Controlling T can control the width of WOUT.

3 Conclusion
The main function of the circuit designed in this paper is to generate a timing signal source. It is similar to the self-timing method. For example, using this signal as the signal source of the control signal, the corresponding control signal can be derived through simple delay, AND, OR operations, and these signals can be used to control various functional modules inside the memory, such as sensitive amplifiers and latches. The characteristic of this circuit is that the width of the timing signal source is controllable. By adjusting the capacitance or charging current, different output pulse widths can be obtained, which can be determined in combination with the width of the control signal required in the memory.