VLSI chip - digital signal testing

As the basis of VLSI chip testing, digital signal testing is already a widely used technology. Various EDA suppliers and ATE suppliers have very mature solutions, including the generation, conversion and actual test operation of functional test simulation vectors, as well as AC/DC parameter testing of chips. As the basis of high-speed signal testing and the cornerstone of chip testing, we will introduce the general digital signal testing technology, difficulties and various solutions in this article, which will be a reference for the high-speed signal testing introduced in the next article.

The most basic digital signal test is the functional test, which is to simulate the actual working state of the chip, input a series of signals, and detect whether the output signal is consistent with the predicted normal output at the output end. Taking the simplest memory unit as an example, input the clock, write signal, address, data, and then input the read signal and address, and finally observe whether the output data is correct at the output end.

To actually apply functional testing on ATE, you need to first have the correct functional simulation test vector (including input vector and expected output vector), and then convert it into the test program of ATE. When running the program, the test channel sends a driving waveform to the chip, compares the actual output vector with the expected output vector, and obtains the Pass/Fail result.

As the scale of VLSI becomes larger and larger, the internal functions become more and more complex, and the functional tests become more and more complex, which results in an increase in the depth of test vectors. The test program of a chip usually has many functional test vectors to simulate different working states and test different functional modules. These vectors will be loaded into the test vector memory and executed in a sequential or concurrent manner. In the actual production process, due to the limitation of memory size, loading a segment of vectors, testing a segment of vectors, and then loading another segment of vectors will greatly increase the test cost, so the right size and easy upgrade are important indicators for measuring ATE systems. With the application of DFT scan testing, the vector depth required for many chip tests has exceeded 20M, and some even reach 100M.

Another problem caused by the increasing complexity of functional testing is the difficulty of debugging. The most direct and simple debugging method is to compare the actual waveform with the expected waveform to determine the status of the problem and find out the cause. The figure below shows the Timing Diagram tool in the SmarTest software. In this page, we can see the 5 input waveforms (including the data input by a pin group) and the waveforms of the 7 output pins. Each waveform here is the waveform actually obtained by the test channel in the 10 cycles we selected, including the shape of each comparison edge and the rising and falling edges of each pulse, and the timing and output voltage can be measured. By comparing such waveforms with the expected waveforms, or even the simulation waveforms of EDA tools, it can be concluded that the functional test failure is caused by logic errors, electrical characteristics problems or other reasons.

With the increasing popularity of SOC design, more and more IPs with different speeds are integrated into the same chip. From high-speed PCI Express, USB2.0 to basic SDRAM, PCI, testing a chip with such a large speed range from 33Mbps to 2.5Gbps puts forward a series of requirements from function to cost for ATE, and also brings a series of challenges from hardware to software. In terms of hardware, requiring each channel to be able to test such a large speed range will inevitably bring expensive testing costs, so a better solution is to flexibly configure the machine according to the requirements of the chip. High-speed and low-speed test channels can exist on the same platform to achieve channel mixing. In terms of software, the clock frequencies of different IPs are different. In order to facilitate debugging and save test vector memory, multi-port technology can be used to convert and test different ports with different clock frequencies. At the same time, it can also be tested in parallel with other ports (concurrent test).

The DC parameter test of digital signal chips mainly measures the electrical characteristics of the chip pins. Common test items include: connectivity, input leakage, high impedance leakage, output current and voltage, etc. Taking the commonly used output voltage as an example, it mainly tests the load capacity of the pin. When the output is low, current is injected and the output voltage is measured. As the injected current increases, the output voltage will also increase. Whether the output voltage can be kept within a certain range under a certain load (injected current) can measure whether the electrical characteristics of this pin are qualified.

If you want to measure the electrical characteristics of multiple output pins at the same time, two conditions are required: (1) a suitable functional test vector sets these output pins to a certain output state at the same time; (2) the test channel corresponding to each output pin has independent drive and test capabilities or PMU (parametric measurement unit).

In addition to the above-mentioned functional tests and DC parameter tests, digital signal chip testing also includes AC parameter tests, power consumption tests, and other items, which will be introduced in later articles. Almost all VLSI chip tests are inseparable from digital signal testing, so although digital signal testing is very mature, it is still the basis for learning chip testing.