Aerospace measurement and control: system-level BIT design and BIT verification technology

System-level BIT is the main means and method for monitoring key system functions, detecting and isolating system-level faults, and is also a key part of testability design. Compared with board-level BIT, system-level BIT requires more complicated information analysis and needs to consider more extensive factors. Therefore, simply using one technology and one structure is far from meeting the requirements, and a combination of multiple key technologies must be used.

The main contents of system-level BIT design technology are system-level BIT architecture technology, intelligent BIT design technology, and false alarm reduction technology. In addition, a very important link in BIT design technology - BIT verification should not be ignored. BIT verification is to inject a certain number of faults into the developed product, use the test method specified in the BIT design to detect and isolate the fault, estimate the testability level of the product according to the results, and judge whether it meets the specified requirements, and decide whether to accept or reject it.

1. System-level BIT architecture

The decentralized and independent conventional BIT structure is no longer suitable for the development of system-level BIT. Therefore, the intelligent BIT in large and complex systems is increasingly adopting distributed, centralized and distributed integrated BIT structures. This is the result of long-term exploration of BIT technology and the requirement of the inherent hierarchical characteristics of electronic systems, reflecting the "parallel design" concept of system development.

1. Distributed BIT

The distributed structure of BIT is that each subsystem has its own microprogram and microdiagnosis. The microprocessor of each subsystem is only responsible for this system and has no relationship with other systems. The microprocessor of each subsystem can make judgments and decisions on the status of this subsystem and finally display the status of the system through the system fault 显示器\'); companyAdEvent.show(this,\'companyAdDiv\',[5,18])"> display .

2. Centralized BIT

Centralized BIT does not set up its own microprogram and microdiagnosis at each subsystem level. The control, diagnosis, and decision-making functions of the entire system are all realized by a microprocessor. Each subsystem only uploads the collected information to the main microprocessor through the data bus. This microprocessor analyzes the received data information and the stored historical information, comprehensively diagnoses the functional status of the entire system, analyzes and evaluates the monitoring system, and makes decisions. At the same time, this status information is output to each display device and stored.

3. Distributed Integrated BIT (HIBIT)

The so-called HIBIT design means that the designed testability mechanism has the same hierarchical structure as the system, that is, it has a hierarchical structure including system level, subsystem level, circuit board level, multi-chip module level and chip level. The testability mechanisms at different levels are connected through the test bus. In essence, HIBIT technology is an extension of boundary scan technology. In HIBIT, board-level testing is carried out using the IEEE 1149.1 boundary scan standard, while device-level and system-level testing is carried out through the IEEE 1149.5 MTM bus.

Hierarchical Integration BIT

2. Intelligent BIT Technology

In the past 20 years, intelligent BIT technology has developed rapidly. At present, there are many intelligent BIT technologies, such as integration, information enhancement, improved decision-making, maintenance history, self-adaptation and temporary storage monitoring.

The above six intelligent BIT technologies are respectively aimed at a specific aspect of the BIT problem, and use AI technologies such as ES (expert system), neural network, finite state automaton, etc., in an attempt to fundamentally improve the false alarm, CND and RTOK problems caused by the backward fault diagnosis algorithm, the inability to use human experience and maintenance history data, and the inability to identify new failure modes not considered in the design in conventional BIT. In practical applications, they can be combined in various ways to form a wider range of BIT improvement methods. For example, on the one hand, information enhancement BIT or improved decision-making BIT can be used in a single subsystem to improve BIT performance; on the other hand, all six methods can be combined to form an intelligent BIT system covering the entire system.

3. Anti-false alarm technology

Due to the fuzziness of BIT diagnosis and insufficient diagnostic ability, the BIT false alarm rate (FAR) is high and intermittent faults cannot be isolated, which seriously reduces the credibility of BIT diagnostic test results and affects the trust of users and maintenance personnel in BIT. Therefore, it is also a current research focus and hotspot to analyze and study the false alarm problem of BIT and propose some methods and measures to solve the false alarm problem of BIT.

1. Causes of BIT false alarms

The main reasons for BIT false alarms can be summarized as follows: defects in BIT design, improper selection of threshold values ​​(or test tolerances), inappropriate fault diagnosis algorithms, and low BIT reliability.

2. BIT false alarm control

In view of the above-mentioned causes of BIT false alarms, a variety of methods can be adopted at various stages of BIT to control BIT false alarms and reduce BIT false alarm rates.

To reduce false alarms from the BIT design scheme, multiple judgments or delayed alarms are performed before the alarm to filter out the instantaneous impact; in order to reduce false alarms caused by tolerance checks, reasonable reliability tolerance design must be carried out. Use BIT detection redundancy technology to vote on faults in the detection structure to reduce the false alarm rate; finally, a complete test and verification plan must be formulated. Whether the BIT design meets the requirements must undergo various tests and verifications.

To reduce the false alarm problem of BIT, it is necessary to establish a perfect system performance model and conduct failure mode impact analysis to timely discover unreliable links in the design and take certain methods to eliminate and isolate the faults.

Reducing BIT false alarm problems from the hardware perspective. It is usually stipulated that the reliability of BIT should be one order of magnitude higher than the failure rate of the test system and equipment. One method is to make the failure rate of the components constituting BIT one order of magnitude higher than the failure rate of the components of the system and equipment. Another method is to stipulate that the number of BIT components in the system should not exceed 10% of the total number of electrical components in the entire system. In addition, BIT system self-diagnosis and system reconstruction level redundant BIT can improve the reliability of BIT itself. On the other hand, various filtering measures are taken to carry out anti-interference design. With the development of optical fiber technology, optical fiber data bus can be used to further improve the reliability of the system and reduce false alarms. In addition, the reliability of components can be improved, high-precision test devices can be used, assembly quality can be improved, production processes can be improved, and designs can be made to resist harsh environmental stress. [page]

Intelligent BIT diagnosis is integrated into the software. Conventional BIT diagnostic algorithms use instantaneous input signals as the basis for judging whether a fault occurs, and do not consider the dynamic historical data of the object being tested. Instantaneous values ​​are not enough to explain the fault condition of the system. Therefore, more effective intelligent fault diagnosis algorithms should be adopted to reduce such misjudgments and better identify intermittent faults in the system. Intelligent BIT technology is the focus of current research in the BIT field, and the United States has included this technology in the key development projects of the 21st century. The research content of intelligent BIT technology includes intelligent design, intelligent detection, intelligent diagnosis and intelligent decision-making. Intelligent BIT does not only rely on internal test information for decision-making, but also combines artificial intelligence technologies such as expert systems and neural networks to conduct comprehensive analysis and diagnosis based on the environmental factors of the system, historical data of BIT and other information, which enhances the decision-making ability of BIT and greatly reduces the probability of false alarms.

4. Fault Injection Technology

Fault injection technology is an important aspect of BIT verification research and the basis for verification work. Fault injection is to inject effective fault mode samples of the system into the physical system to evaluate the testability design level of the system. Through fault injection, the deficiencies of the system testability design can be exposed and discovered early, and effective measures can be taken to improve the test diagnosis capability.

Prototype-based fault injection methods are usually further divided according to the implementation method of fault injection, which can be divided into hardware-implemented, software-implemented, and physically-implemented fault injection techniques.

Hardware fault injection technology mainly uses additional hardware devices to inject faults into the target system. The additional hardware devices are connected to the target system through probes, chip sockets, etc. Due to the restrictions on the access points to the target prototype, most of the current research on hardware-implemented fault injection is focused on the chip pin level.

Software fault injection technology is to simulate the error status of system software and hardware through a specific program . This method is easy to expand new fault types. Fault injection is originally to simulate the occurrence of hardware or software faults by modifying program execution statements, adding, modifying, deleting data or directly modifying the contents of registers or memories .

Generally speaking, the process of fault injection can be divided into four steps: selecting a fault model, performing fault injection, monitoring system behavior, and analyzing fault results. Among them, selecting a fault model and analyzing fault results are processes of interaction with the user, which are carried out under the control of the user, while performing fault injection and monitoring system behavior are automatically performed by the system after the user selects a fault model for fault injection, which is a direct interface with the target system.

Aerospace Measurement and Control The company has conducted in-depth research on various key technologies of system-level BIT and transformed these technologies into the design and development process of multiple projects. At the same time, a set of system-level BIT auxiliary design tools has been developed and constructed. Through this platform, a series of testability analyses can be performed on the system under test, and multiple work suggestions for BIT design can be given based on the analysis results. After the design is completed, the effectiveness of the BIT design can be verified by fault injection. The research results of Aerospace Measurement and Control Company in system-level BIT design and the software platform developed can standardize the system-level BIT design work and greatly improve the efficiency of BIT design.